參數(shù)資料
型號(hào): SI5324C-C-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 13/72頁
文件大小: 0K
描述: IC CLOCK MULT 2KHZ-346MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5324
20
Rev. 1.1
The Si5324 has two differential clock outputs. The
signal format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. When configured for CMOS, four clock
outputs are available. If not required, the second clock
output can be powered down to minimize power
consumption. In addition, the phase of one output clock
may be adjusted in relation to the phase of the other
output clock. The resolution varies from 800 ps to 2.2 ns
depending on the PLL divider settings. The DSPLL
sim
software utility determines the phase offset resolution
for a given combination of input clock and multiplication
ratio. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply with best-
in-class PSNR.
3.1. External Reference
An external, high quality 38.88 MHz clock or a low-cost
114.285 MHz 3rd overtone crystal or external reference
is used as part of a fixed-frequency oscillator within the
DSPLL. This external reference is required for the
device
to
perform
jitter
attenuation.
Specific
recommendations can be found in the Family Reference
Manual.
In digital hold, the DSPLL remains locked and tracks the
external reference. Note that crystals can have
temperature sensitivities.
Due to the low bandwidth capabilities of this part, any
low-frequency wander or instability on the external
reference will transfer to the output clocks. To address
this issue, a stable external reference, TXCO, OCXO, or
thermally-isolated crystal is recommended.
For example, with a 20 ppm oscillator as the reference
on the XA/XB pins, temperature changes cause the
oscillator to change frequency slightly. Although the
Si5324 is locked to its input on CLKIN, it also uses the
XA/XB as a reference.
If there is a need to use a reference oscillator instead of
a crystal, Silicon Labs does not recommend using
MEMS
based oscillators.
Instead,
Silicon
Labs
recommends the Si530EB121M109DG, which is a very
low-jitter/wander, LVPECL, 2.5 V crystal oscillator. The
very low loop BW of the Si5324 means that it can be
susceptible to XAXB reference sources that have high
wander. Experience has shown that in spite of having
low jitter, some MEMs oscillators have high wander, and
these devices should be avoided. Contact Silicon Labs
for details.
3.2. Additional Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5324. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon Laboratories offers a PC-based software utility
called DSPLL
sim to simplify device configuration,
including frequency planning and loop bandwidth
selection. The FRM and this utility can be downloaded
from http://www.silabs.com/timing (see “AN803: Lock and
Settling Time Considerations for Si5324/27/69/74 Any-
Frequency Jitter Attenuating Clock ICs” for additional details)
.
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