(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%," />
參數(shù)資料
型號: SI5324C-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 72/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-346MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5324
Rev. 1.1
9
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XARIN
RATE[1:0] = LM, ML, MH,
or HM, ac coupled
—12
k
Input Voltage Swing
XAVPP
RATE[1:0] = LM, ML, MH,
or HM, ac coupled
0.5
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XBVPP RATE[1:0] = LM, ML, MH,
or HM
0.5
2.4
VPP
CKINn Input Pins
Input Frequency
CKNF
0.002
710
MHz
Input Duty Cycle
(Minimum Pulse Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
40
60
%
2—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not configured
for CMOS or
Disabled)
CKOF
N1
60.002
945
MHz
N1 = 5
970
1134
MHz
N1 = 4
1.213
1.4
GHz
Maximum Output
Frequency in CMOS
Format
CKOF
212.5
MHz
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT
setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency
Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding
the lock time of your frequency plan.
3. LOCKT = 3.3 ms
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