參數(shù)資料
型號(hào)： SI5324C-C-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 58/72頁
文件大?。?/td> 0K
描述： IC CLOCK MULT 2KHZ-346MHZ 36VQFN
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類型： 時(shí)鐘/頻率倍增器，抖動(dòng)衰減器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)（WAN），SONET/SDH/STM，視頻
輸入： 時(shí)鐘
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 346MHz
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤
Si5324
Rev. 1.1
61
4C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for
CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
5, 10, 32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following Vdd pins:
50.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to the device as is practical.
7
6
XB
XA
IAnalog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by RATE[1:0] pins.
8, 31, 20,
19
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to VDD/2.
H setting corresponds to VDD.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
13
CKIN2+
CKIN2–
IMulti
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Pin #
Pin Name I/O Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
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SI5324C-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5324D-C-GM 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Prec.Clk Mult/Jitter Atten. 2kHz-150MHz RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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SI5324E-C-GM 制造商:Silicon Laboratories Inc 功能描述:ANYRATE PRECISION CLOCK - Trays
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