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參數(shù)資料
| 型號(hào)： | SI5323-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIPLIER/ATTENUATOR 36-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
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Si5323
30
Rev. 1.0
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock
indicator.
0 = PLL locked
1 = PLL unlocked
19
DEC
I
LVCMOS
Skew Decrement.
A pulse on this pin decreases the input to output device skew
by 1/fOSC (approximately 200 ps). There is no limit on the
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
20
INC
I
LVCMOS
Skew Increment.
A pulse on this pin increases the input to output device skew
by 1/fOSC (approximately 200 ps). There is no limit on the
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
Note:
If NI_HS = 4, increment is not available.
This pin has a weak pull-down.
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B41-MY-F3 | CONVERTER MOD DC/DC 12V 50W |
| VE-B1Z-MY-F1 | CONVERTER MOD DC/DC 2V 20W |
| VE-B1Z-MX-F4 | CONVERTER MOD DC/DC 2V 30W |
| VE-B1Z-MW-F1 | CONVERTER MOD DC/DC 2V 40W |
| VE-B1Y-MY-F4 | CONVERTER MOD DC/DC 3.3V 33W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5323-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Ctrl Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5323-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5324 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5324A-C-GM | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Prec.Clk Mult/Jitter Atten. 2kHz-1.4 GHz RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5324A-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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