Si5323
10
Rev. 1.0
Table 4. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CKIN Input Pins
Input Frequency
CKNF
.008
—
710
MHz
Input Duty Cycle (Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40%/60% limitation
applies only to high clock
frequencies)
40
—
60
%
2—
—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable)
CKOF
.008
—
710
MHz
Maximum Output Frequency in
CMOS Format
CKOFMC
—
212.5
MHz
Single-ended Output Rise/Fall
(20–80%)
CKOTRF
CMOS Output
VDD =1.71
Cload = 5 pF
——
8
ns
CMOS Output
VDD =2.97
Cload = 5 pF
——
2
ns
Differential Output Rise/Fall Time
CKOTRF 20 to 80 %, fOUT = 622.08
—
230
350
ps
Output Duty Cycle Differential
Uncertainty
CKODC
100
Load
Line to Line
Measured at 50% Point
(not for CMOS)
——
±40
ps
LVCMOS Input Pins
Minimum Reset Pulse Width
tRSTMIN
1—
—
s
Input Capacitance
CIN
——
3
pF
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD =20pf
—25
—
ns
LOSn Trigger Window
LOSTRIG From last CKIN to LOS
—750
s
Time to Clear LOL after LOS Cleared tCLRLOL
fin unchanged and XA/XB
stable.
LOS to LOL
—10
—
ms