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參數(shù)資料
| 型號： | SI5323-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIPLIER/ATTENUATOR 36-QFN |
| 標準包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
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Si5323
Rev. 1.0
29
4C2B
O
LVCMOS
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once
triggered, the alarm will remain active until CKIN2 is
validated.
0 = CKIN2 present
1 = LOS on CKIN2
5, 10,
32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following VDD pins:
5
0.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to device as is
practical.
7
6
XB
XA
IAnalog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. Refer to Family
Reference Manual for interfacing to an external reference.
External reference must be from a high-quality clock source
(TCXO, OCXO). Frequency of crystal or external clock is set
by the RATE pins.
8, 31
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
9
AUTOSEL
I
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
selection to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
Refer to the Family Reference Manual for settings. These
pins have both a weak pull-up and a weak pull-down and
default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
12
13
CKIN2+
CKIN2–
I
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相關PDF資料 |
PDF描述 |
|---|---|
| VE-B41-MY-F3 | CONVERTER MOD DC/DC 12V 50W |
| VE-B1Z-MY-F1 | CONVERTER MOD DC/DC 2V 20W |
| VE-B1Z-MX-F4 | CONVERTER MOD DC/DC 2V 30W |
| VE-B1Z-MW-F1 | CONVERTER MOD DC/DC 2V 40W |
| VE-B1Y-MY-F4 | CONVERTER MOD DC/DC 3.3V 33W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5323-C-GMR | 功能描述:時鐘合成器/抖動清除器 Pin-Ctrl Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5323-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5324 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5324A-C-GM | 功能描述:時鐘合成器/抖動清除器 Prec.Clk Mult/Jitter Atten. 2kHz-1.4 GHz RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5324A-C-GMR | 功能描述:時鐘合成器/抖動清除器 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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