參數(shù)資料
型號: SI5321-H-GL
廠商: Silicon Laboratories Inc
文件頁數(shù): 26/34頁
文件大?。?/td> 0K
描述: IC CLOCK MULT SONET/SDH 63LFBGA
標準包裝: 260
系列: DSPLL®
類型: 時鐘乘法器
PLL:
輸入: LVTTL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.8GHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -20°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 63-LBGA
供應商設備封裝: 63-PBGA(9x9)
包裝: 托盤
Si5321
32
Rev. 2.5
6. 9x9 mm PBGA Card Layout
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 m minimum, all the way around the pad.
Stencil Design
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2.
The stencil thickness should be 0.125 mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1.
A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Symbol
Min
Nom
Max
X
0.40
0.45
0.50
C1
7.00
C2
7.00
E1
1.00
E2
1.00
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相關代理商/技術參數(shù)
參數(shù)描述
SI5321-H-ZL2 制造商:Silicon Laboratories Inc 功能描述:
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SI5322 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock
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