參數(shù)資料
型號(hào)： SI5321-H-GL
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 20/34頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK MULT SONET/SDH 63LFBGA
標(biāo)準(zhǔn)包裝： 260
系列： DSPLL®
類型： 時(shí)鐘乘法器
PLL： 是
輸入： LVTTL
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.8GHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -20°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 63-LBGA
供應(yīng)商設(shè)備封裝： 63-PBGA（9x9）
包裝： 托盤
Si5321
Rev. 2.5
27
B1
C1
BWSEL[0]
BWSEL[1]
I*
LVTTL*
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note:
The loop filter bandwidth is twice the value
indicated here when BWBOOST is set high.
D2
BWBOOST
I*
LVTTL*
Bandwidth Boost.
Active high input to boost the selected bandwidth
2x. When this pin is high the loop filter bandwidth
selected on BWSEL[1:0] is doubled. When this pin
is high, FXDDELAY must also be high and FEC[2:0]
must be 000.
B4
FXDDELAY
I*
LVTTL*
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications
that require a known or constant input-to-output
phase relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from Digital
Hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
“phase build out” to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized.
In this case, the input-to-output phase relationship
following the transition out of digital hold mode is
determined by the phase relationship at the time
that switching occurs.
Note:
FXDDELAY should remain at a static high or static
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin
is low. FXDDELAY must be set high when
BWBOOST is set high.
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5321-H-ZL2 制造商:Silicon Laboratories Inc 功能描述:
Si5321-XLNX-DC 功能描述:子卡和OEM板 Silabs/Xilinx Ref Design RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
SI5322 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock
Si5322/23-EVB 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5322/Si5323 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
Si5322-B-GM 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 1 OUT RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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