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參數(shù)資料
| 型號： | SI5321-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULT SONET/SDH 63LFBGA |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | LVTTL |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.8GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 63-LBGA |
| 供應(yīng)商設(shè)備封裝： | 63-PBGA（9x9） |
| 包裝： | 托盤 |
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Si5321
Rev. 2.5
25
Table 10. Si5321 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
D1
E1
CLKIN+
CLKIN–
I
AC Coupled
200–500 mVPPD
(See Table 2)
System Clock Input.
Clock input to the DSPLL circuitry. The frequency of
the CLKIN signal is multiplied by the DSPLL to gen-
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the INFRQ-
SEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor may be selected for FEC operation
using the FEC[2:0] control pins.
F1
G1
H1
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
I*
LVTTL*
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 38 MHz range.
011 = 77 MHz range.
100=155MHz range.
101=311MHz range.
110 = 622 MHz range.
111 = Reserved.
H6
H7
CLKOUT+
CLKOUT–
OCML
Differential Clock Output.
High-frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multipli-
cation factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19, 38, 77, 155,
311, 622, 1244 or 2488 MHz range as indicated in
Table 3 on page 7. The clock output frequency is
selected using the FRQSEL[2:0] pins. The clock
input frequency is selected using the INFRQ-
SEL[2:0] pins. An additional scaling factor may be
selected for FEC operation using the FEC[2:0] con-
trol pins.
*Note:
The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5321-H-ZL2 | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5321-XLNX-DC | 功能描述:子卡和OEM板 Silabs/Xilinx Ref Design RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI5322 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5322/23-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5322/Si5323 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| Si5322-B-GM | 功能描述:時鐘合成器/抖動清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 1 OUT RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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