Si5319
Rev. 1.0
11
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20pf
—25
—
ns
LOSn Trigger Window
LOSTRIG
From last CKINn
to
Internal detection of LOSn
N3 ≠ 1
—
4.5 x N3
TCKIN
Time to Clear LOL
after LOS Cleared
tCLRLOL
LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—10
—
ms
Device Skew
Input to Output Phase
Change Due to Tem-
perature Variation
tTEMP
Max phase changes from
–40 to +85 °C
—300
500
ps
PLL Performance
(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)
Lock Time
tLOCKMP
Start of ICAL to
of LOL
—
35
1200
ms
Output Clock Phase
Change
tP_STEP
After clock switch
f3
128 kHz
—200
—
ps
Closed Loop Jitter
Peaking
JPK
—0.05
0.1
dB
Jitter Tolerance
JTOL
Jitter Frequency
Loop
Bandwidth
5000/BW
—
ns pk-pk
Phase Noise
fout = 622.08 MHz
CKOPN
1 kHz Offset
—
–106
–87
dBc/Hz
10 kHz Offset
—
–121
–100
dBc/Hz
100 kHz Offset
—
–132
–104
dBc/Hz
1 MHz Offset
—
–132
–119
dBc/Hz
Subharmonic Noise
SPSUBH
Phase Noise @ 100 kHz
Offset
—–88
–76
dBc
Spurious Noise
SPSPUR
Max spur @ n x F3
(n
1, n x F3 < 100 MHz)
—–93
–70
dBc
Table 4. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit