參數(shù)資料
型號： SI5319-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 1/50頁
文件大?。?/td> 0K
描述： BOARD EVALUATION SI5319
標(biāo)準(zhǔn)包裝： 1
主要目的： 計時，時鐘乘法器
嵌入式： 否
已用 IC / 零件： SI5319
主要屬性： 1 輸入，1 輸出
次要屬性： CML，CMOS，LVDS，LVPECL
已供物品： 板，CD，文檔
Rev. 1.0 12/10
Copyright 2010 by Silicon Laboratories
Si5319
Features
Generates any frequency from 2 kHz to 945 MHz and
select frequencies to 1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock output with jitter generation as low as
0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60Hz to 8.4kHz)
Meets OC-192 GR-253-CORE jitter specifications
Clock or crystal input with manual clock selection
Selectable clock output signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom OTN FEC ratios (e.g.
255/238, 255/237, 255/236)
Supports various frequency translations for Synchronous
Ethernet
LOL, LOS alarm outputs
I2C or SPI programmable
On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or
3.3 V ±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
10G/40G/100G OTN line cards
SONET/SDH OC-48/STM-16 and OC-192/STM-64
line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
DSLAM/MSANs
Test and measurement
Broadcast video
Discrete PLL replacement
Description
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The
Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock
generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input
clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5319 is based on Silicon
Laboratories' third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is
digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
DSPLL
Loss of Signal
Xtal or Refclock
CKIN
CKOUT
÷ N31
÷ N2
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Lock
Xtal/Clock Select
I
2C/SPI Port
Control
÷ N32
XO
÷ NC1_LS
N1_HS
Rate Select
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
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