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參數(shù)資料
| 型號： | SI5311 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC |
| 中文描述： | 精密高速時鐘倍頻/再生器集成電路 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 513K |
| 代理商： | SI5311 |
Si5311
Preliminary Rev. 0.6
21
12, 13
CLKOUT–,
CLKOUT+
O
CML
Differential Clock Output.
The clock output signal is a regenerated version of
the input clock signal present on CLKIN. It is phase
aligned with MULTOUT and is updated on the rising
edge of MULTOUT.
Notes:
The CLKOUT output is not valid for MULTSEL[1:0]
= 00 or MULTSEL[1:0] = 01. The CLKOUT output
is also not valid for MULTOUT:CLKIN ratios of 1:1
(MULTOUT = 1x CLKIN).
Connection of an improperly terminated
transmission line to the CLKOUT output can
cause reflections that may adversely affect the
performance of the MULTOUT output. If the
CLKOUT output is not used, these pins should be
either tied to V
DD
(recommended), left
unconnected, or connected to a properly
terminated transmission line.
15
PWRDN/CAL
I
LVTTL
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion" on page 18.)
Note:
This input has a weak internal pulldown.
16, 17
MULTOUT–,
MULTOUT+
O
CML
Differential Multiplier Output.
The multiplier output is generated from the signal
present on CLKIN. In the absence of CLKIN, the
REFCLK is used to bound the frequency of MUL-
TOUT according to Table 4 on page 8.
Note:
Connection of an improperly terminated
transmission line to the MULTOUT output can
cause reflections that may adversely affect the
CLKOUT output. If the MULTOUT output is not
used, these pins should be either tied to V
DD
(recommended), left unconnected, or connected
to a properly terminated transmission line.
19
MULTSEL1,
MULTSEL0
I
LVTTL
Multiplier Rate Select.
These pins configure the onboard PLL-based clock
multiplier for clock generation at one of four user
selectable clock rates.
Note:
These inputs have weak internal pulldowns.
20
NC
No Connect.
This pin should be tied to ground.
Table 13. Si5311 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5311-BM | BAIL MOUNT/100 BULK PKG |
| SI5312-H(B) | IRED |
| SI5312-H | IRED |
| SI5312-HB | IRED |
| SI5313-C(B) | IRED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI53112-A00AGM | 功能描述:IC BUFFER ZDB PCIE 1:12 64-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：12 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53112-EK | 功能描述:Si53112 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53112 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| SI53115-A01AGM | 功能描述:IC BUFFER ZDB PCIE 1:15 64-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：15 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53119-A01AGM | 功能描述:IC BUFFER ZDB PCIE 1:19 72-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：19 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤 供應(yīng)商器件封裝:72-QFN（10x10） 標(biāo)準(zhǔn)包裝:168 |
| SI53119-EK | 功能描述:Si53119 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53119 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
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