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參數(shù)資料
| 型號： | SI5311-BM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | BAIL MOUNT/100 BULK PKG |
| 中文描述： | 精密高速時鐘倍頻/再生器集成電路 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 513K |
| 代理商： | SI5311-BM |
Preliminary Rev. 0.6 6/01
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Copyright 2001 by Silicon Laboratories
Si5311-DS06
Si5311
P
RECISION
H
IGH
S
PEED
C
LOCK
M
ULTIPLIER
/R
EGENERATOR
IC
Features
Complete precision high speed clock multiplier and regenerator device:
Applications
Description
The Si5311 is a fully integrated high-speed clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. When the clock multiplier is operating in
either the 150–167 MHz range or the 600–668 MHz range, the clock
regenerator operates simultaneously. The clock regenerator creates a
“clean” version of the input clock by using the clock synthesis phase-
locked loop (PLL) to remove unwanted jitter and square up the input
clock’s rising and falling edges. The Si5311 uses Silicon Laboratories
patented DSPLL
architecture to achieve superior jitter performance while
eliminating the analog loop filter found in traditional PLL designs.
The Si5311 represents a new standard in low jitter, small size, low power,
and ease-of-use for high speed clock devices. It operates from a single
2.5 V supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
!
Performs Clock Multiplication to
One of Four Frequency Ranges:
150–167 MHz, 600–668 MHz,
1.2–1.33 GHz, or 2.4–2.67 GHz
!
Jitter Generation as low as
0.5 ps
RMS
for 622 MHz Output
!
Accepts Input Clock from
9.4–668 MHz
!
Regenerates a “Clean”, Jitter-
Attenuated Version of Input
Clock
!
DSPLL Technology Provides
Superior Jitter Performance
!
Small Footprint: 4 mm x 4 mm
!
Low Power: 310 mW typical
!
SONET/SDH Systems
!
Terabit Routers
!
Digital Cross Connects
!
Optical Transceiver Modules
!
Gigabit Ethernet Systems
!
Hybrid VCO Modules
DSPLL
TM
Phase-Locked
Loop
BUF
BUF
CLKIN+
CLKIN–
2
M ULTSEL1–0
REFCLK+
REFCLK–
2
2
2
LOL
M ULTOUT+
M ULTOUT–
CLKOUT+
CLKOUT–
Bias Gen
REXT
BUF
Calibration
Regeneration
PW RDN/CAL
2
Ordering Information:
See page 22.
Pin Assignments
Si5311
1
2
3
4
5
6
7
8
9
13
14
15
16
REXT
VDD
GND
REFCLK+
REFCLK–
PWRDN/CAL
VDD
CLKOUT+
CLKOUT–
VDD
12
11
10
GND
Pad
17
18
19
20
M
M
G
M
M
L
V
G
C
Top View
P
RELIMINARY
D
ATA
S
HEET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5312-H(B) | IRED |
| SI5312-H | IRED |
| SI5312-HB | IRED |
| SI5313-C(B) | IRED |
| SI5313-C | IRED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5311-H | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5311-H(B) | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5311-HB | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5312-H | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5312-H(B) | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
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