- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373395 > SI5311 (Electronic Theatre Controls, Inc.) PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC PDF資料下載
參數(shù)資料
| 型號(hào)： | SI5311 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC |
| 中文描述： | 精密高速時(shí)鐘倍頻/再生器集成電路 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 513K |
| 代理商： | SI5311 |
Si5311
Preliminary Rev. 0.6
17
with the input clock. During reacquisition, the multiplier
output (MULTOUT) will drift over a range of
approximately 1% relative to the supplied reference
clock. The LOL output will remain asserted until the
divided multiplier output frequency differs from the
REFCLK frequency by less than the amount specified in
Table 4.
Note:
LOL is not asserted during PWRDN/CAL.
PLL Performance
The Si5311 DSPLL circuitry is designed to provide low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking. Each
of these key performance parameters is described more
fully in the following sections.
Jitter Tolerance
Jitter tolerance for the Si5311 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
added to the incoming clock before the PLL exceeds its
allowable operating range and loses lock. The tolerance
is a function of the jitter frequency, the incoming clock
rate, and the MULTSEL0/1 settings.
The jitter tolerance for specified jitter frequencies and
input clock rates is given in Tables 5, 6, 7, and 8.
Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that will be passed on to the Si5311
CLKOUT and MULTOUT outputs. The DSPLL
technology used in the Si5311 provides a tightly
controlled jitter transfer curve because many of the PLL
gain parameters are determined by digital signal
processing algorithms which do not vary over supply
voltage, process, and temperature. In a system
application, a well-controlled transfer curve minimizes
the output clock jitter variation from board to board,
providing
more
consistent
performance.
The jitter transfer characteristic is a function of the
MULTSEL0/1 settings and the input clock rate. Higher
input clock rates produce higher bandwidth transfer
functions with lower jitter peaking. Table 4 gives the
3 dB bandwidth and peaking values for specified input
clock rates and MULTSEL0/1 settings. Figures 6, 7, 8,
and 9 show a family of jitter transfer curves for different
input clock rates.
Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
a function of MULTSEL0/1 settings and input clock
frequency. For clock multiplier applications, the higher
system
level
jitter
the multiplier ratio desired, the larger the jitter
generation. Table 4 gives the jitter generation values for
specified MULTSEL0/1 settings and input clock rates.
Figure 6. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 00
(MULTOUT = 2400–2672 MHz)
Figure 7. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 01
(MULTOUT = 1200–1336 MHz)
10
3
10
4
10
5
10
6
9
8
7
6
5
4
3
2
1
0
PLL Jitter Transfer Functions (MULTSEL[1:0]=00) (dB)
CLKIN=622MHz
10
3
10
4
10
5
10
6
9
8
7
6
5
4
3
2
1
0
PLL Jitter Transfer Functions (MULTSEL[1:0]=01) (dB)
CLKIN=311MHz
CLKIN=622MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5311-BM | BAIL MOUNT/100 BULK PKG |
| SI5312-H(B) | IRED |
| SI5312-H | IRED |
| SI5312-HB | IRED |
| SI5313-C(B) | IRED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI53112-A00AGM | 功能描述:IC BUFFER ZDB PCIE 1:12 64-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時(shí)鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：12 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53112-EK | 功能描述:Si53112 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53112 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| SI53115-A01AGM | 功能描述:IC BUFFER ZDB PCIE 1:15 64-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時(shí)鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：15 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53119-A01AGM | 功能描述:IC BUFFER ZDB PCIE 1:19 72-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時(shí)鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：19 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤 供應(yīng)商器件封裝:72-QFN（10x10） 標(biāo)準(zhǔn)包裝:168 |
| SI53119-EK | 功能描述:Si53119 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53119 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。