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參數(shù)資料
| 型號： | SI5022 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP |
| 中文描述： | 多速率SONET / SDH的CDR集成電路限幅放大器 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 399K |
| 代理商： | SI5022 |
Si5022/Si5023
18
Preliminary Rev. 0.46
7
LOL
O
LVTTL
Loss-of-Lock.
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
Lock-to-Reference.
When this pin is low, the DSPLL will disregard the
data inputs. If an external reference is supplied, the
output clock will be locked to the supplied refer-
ence. If no external reference is used, the DSPLL
will lock the control loop until LTR is released.
Note:
This input has a weak internal pull-up.
Loss-of-Signal.
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. The LOS
state will nominally have 3 dB of hysteresis relative
to the level set on LOS_LVL. (LOS operation is
guaranteed only when ac coupling is used on the
clock input.)
Data Squelch.
When driven high, this pin forces the data present
on DOUT to zero. For normal operation, this pin
should be low. DSQLCH can be used during LOS/
LOL conditions to prevent random data from being
presented to the system.
Note:
This input has a weak internal pull-down.
Supply Voltage.
Nominally 2.5 V for Si5022 and 3.3 V for Si5023.
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. ac coupling is recom-
mended.
Production Test Input.
This pin is used during production testing and
must
be tied to GND for normal operation.
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
8
LTR
I
LVTTL
9
LOS
O
LVTTL
10
DSQLCH
LVTTL
11,14,18,21,
25
VDD
2.5 V or
3.3 V
12,13
DIN+,
DIN–
I
See Table 2
15
TDI
I
LVTTL
16,17
DOUT+,
DOUT–
O
CML
Table 9. Si5022/23 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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