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參數(shù)資料
| 型號： | SI5022 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP |
| 中文描述： | 多速率SONET / SDH的CDR集成電路限幅放大器 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 399K |
| 代理商： | SI5022 |
Si5022/Si5023
Preliminary Rev. 0.46
17
Pin Descriptions: Si5022/23
Figure 13. Si5022/23 Pin Configuration
Table 9. Si5022/23 Pin Descriptions
Pin #
1,2
Pin Name
RATESEL0,
RATESEL1
I/O
I
Signal Level
LVTTL
Description
Data Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Note:
These inputs have weak internal pull-ups.
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 12 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 500 mV.
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie these pins to ground to config-
ures the DSPLL to operate without an external ref-
erence clock.
See Table 8 for typical reference clock frequencies.
3
LOS_LVL
I
4
SLICE_LVL
I
5,6
REFCLK+,
REFCLK–
I
See Table 2
1
RATESEL0
GND
Pad
Top View
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK-
LOL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT-
TDI
N
B
B
V
C
C
C
L
L
D
V
D
D
V
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