![](http://datasheet.mmic.net.cn/300000/Si5022-BM_datasheet_16211382/Si5022-BM_1.png)
Preliminary Rev. 0.46 5/01
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Copyright 2001 by Silicon Laboratories
Si5022/23-DS046
Si5022/Si5023
P
RELIMINARY
D
ATA
S
HEET
M
ULTI
-R
ATE
SONET/SDH CDR IC
WITH
L
IMITING
A
MP
Features
H
igh Speed Clock and Data Recovery device with Integrated Limiting Amp:
Applications
Description
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL
technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
!
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
!
DSPLL Technology
!
Low Power—370 mW (TYP)
!
Small Footprint: 5 mm x 5 mm
!
Bit-Error-Rate Alarm
!
External Reference Not Required
!
Jitter Generation 3.0 mUI
RMS
(TYP)
!
Loss-of-signal Level Alarm
!
Data Slicing Level Control
!
10 mV
PP
Differential Sensitivity
!
2.5 V (Si5022) or 3.3 V (Si5023) Supply
!
!
!
!
SONET/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Gigabit Ethernet Interfaces
!
!
!
!
SONET/SDH Test Equipment
Optical Transceiver Modules
SONET/SDH Regenerators
Board Level Serial Links
Limiting
AMP
DSPLL
TM
Phase-Locked
Loop
BUF
BUF
Retimer
DIN+
DIN–
LOS_LVL
SLICE_LVL
LOS
2
2
2
LOL
CLKOUT+
CLKOUT–
DOUT+
DOUT–
CLKDSBL
Bias Gen
REXT
Squelch
Control
DSQLCH
RESET/CAL
BER_ALM
RATSEL[1:0]
2
REFCLK+
REFCLK–
(Optional)
LTR
BER_LVL
Control
Ordering Information:
See page 14.
Pin Assignments
Si5022/23
1
RATESEL0
GND
Pad
Top View
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
TDI
N
B
B
V
C
C
C
L
L
D
V
D
D
V