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參數資料
| 型號： | SI5020-BM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC |
| 中文描述： | SiPHY多速率SONET / SDH的時鐘和數據恢復芯片 |
| 文件頁數： | 12/18頁 |
| 文件大小： | 335K |
| 代理商： | SI5020-BM |
Si5020
12
Preliminary Rev. 0.8
Figure 7. Jitter Transfer Specification
Power Down
The Si5020 provides a power down pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven “high”, the positive
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100
on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
When PWRDN/CAL is released (set to “l(fā)ow”) the digital
logic resets to a known initial condition, recalibrates the
DSPLL, and will begin to lock to the data stream.
Device Grounding
The Si5020 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 10 and 11 for the ground (GND)
pad location.
Bias Generation Circuitry
The Si5020 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces
power
consumption
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k
(1%) resistor
connected between REXT and GND.
Differential Input Circuitry
The Si5020 provides differential inputs for both the high
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 8. In applications where direct DC
coupling is possible, the 0.1
μ
F capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
versus
traditional
Figure 8. Input Termination for DIN and REFCLK (AC Coupled)
SONET
Data Rate
OC-48
OC-12
OC-3
Fc
(kHz)
2000
500
130
Jitter
Transfer
Fc
Frequency
0.1 dB
20 dB / Decade
Slope
Acceptable
Range
2.5 k
2.5 k
10 k
10 k
102
Si5020
VDD
GND
Zo = 50
Zo = 50
0.1
μ
F
0.1
μ
F
DIN+,
REFCLK+
DIN–,
REFCLK–
Differential Driver
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SI5020-BMR | 功能描述:計時器和支持產品 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020C-BA | 功能描述:時鐘和定時器開發(fā)工具 Multi-Rate SONET/ SDH CDR Morph Board RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5020C-BAR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5020-EVB | 功能描述:時鐘和定時器開發(fā)工具 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI-50210-F | 功能描述:CONN MAGJACK 1PT 10/100BTX G/Y RoHS:是 類別:連接器，互連式 >> 模塊 - 帶磁性元件的插座 系列:MagJack® ST SI-50000 標準包裝:63 系列:Mag45 連接器類型:RJ45 端口數:1 行數:1 安裝類型:面板安裝，通孔，直角 速度:10/100 Base-T 板上方高度:0.555"（14.10mm） LED 顏色:綠 - 綠 每一插座芯體的數目:5 屏蔽:屏蔽 翼片方向:上 特點:板鎖 包裝:托盤 |
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