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參數(shù)資料
| 型號(hào)： | SI5020-BM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC |
| 中文描述： | SiPHY多速率SONET / SDH的時(shí)鐘和數(shù)據(jù)恢復(fù)芯片 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 335K |
| 代理商： | SI5020-BM |
Si5020
Preliminary Rev. 0.8
11
Forward Error Correction (FEC)
The Si5020 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.70 Gbps data rate, the required
reference clock would be 168.75 MHz, 84.375 MHz, or
21.09 MHz.
Lock Detect
The Si5020 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided down version of the recovered clock with the
frequency of the supplied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 8, the PLL is declared out of lock, and the loss-of-
lock (LOL) pin is asserted “high.” In this state, the
DSPLL will periodically try to reacquire lock with the
incoming data stream. During reacquisition, the
recovered clock, CLKOUT, will drift over a ±600 ppm
range relative to the supplied reference clock. The LOL
output will remain asserted until the recovered clock
frequency is within the REFCLK frequency by the
amount specified in Table 4.
Note:
LOL is not asserted during PWRDN/CAL.
PLL Performance
The PLL implementation used in the Si5020 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5020’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 6. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note:
There are no entries in the mask table for the data rate
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
Figure 6. Jitter Tolerance Specification
Jitter Transfer
The Si5020 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 7). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 6.
Jitter Generation
The Si5020 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5020 typically generates less than 3.0 mUI rms of
jitter when presented with jitter-free input data.
Sinusoidal
Input
Jitter (UI p-p)
15
1.5
0.15
f0
f1
f2
f3
ft
SONET
Data Rate
OC-48
OC-12
OC-3
F0
(Hz)
10
10
10
F1
(Hz)
600
30
30
F2
(Hz)
6000
300
300
F3
(kHz)
100
25
6.5
Ft
(kHz)
1000
250
65
Frequency
Slope = 20 dB/Decade
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