參數(shù)資料
型號(hào): SI4022-A0-FT
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/20頁
文件大?。?/td> 726K
描述: IC TX FSK UNI 868/915MHZ 16TSSOP
標(biāo)準(zhǔn)包裝: 96
頻率: 868MHz,915MHz
應(yīng)用: ISM
調(diào)制或協(xié)議: FSK
數(shù)據(jù)傳輸率 - 最大: 115.2kbps
功率 - 輸出: 6dBm
電流 - 傳輸: 24mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
14
Si4022
bw1    bw0
PLL bandwidth
0
0
15 kHz
0
1
30 kHz
1
0
60 kHz
1
1
120 kHz
 
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
1
0
1
1
0
0
0
0     exlp   ctls     0     dcal   bw1   bw0    dsfi    ewi
B0CAh
 
FFIT
The number of data bits in the FIFO has gone below the preprogrammed limit
FFEM
FIFO is empty
FFOV
FIFO overflow
LBD
Low battery detect, the power supply voltage is below the preprogrammed limit
WK-UP
Wake-up timer overflow
POR
Power-on reset
 
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
 
Status Register Read Command
With this command, it is possible to read the status register of the chip through the SDO pin.
Status Register Read Sequence
Extended Features Command:
Bit 7 <exlp>:
Enables low power mode for the crystal oscillator.
Bit 6 <ctls>:
Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128.
Bit 4 <dcal>:
Disables the wake-up timer autocalibration.
Bit 3-2 <bw1:bw0>: Select the bandwidth of the PLL.
Bit 1 <dsfi>:
Disables autosleep on FIFO interrupt if set to 1.
Bit 0 <ewi>:
Enables the automatic wake-up on any interrupt event.
nSEL
SCK
SDI
SDO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
status out
FFIT
FFEM
FFOV
LBD
WK-UP
POR
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