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參數(shù)資料
| 型號(hào)： | SI4022-A0-FT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 726K |
| 描述： | IC TX FSK UNI 868/915MHZ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 頻率： | 868MHz，915MHz |
| 應(yīng)用： | ISM |
| 調(diào)制或協(xié)議： | FSK |
| 數(shù)據(jù)傳輸率 - 最大： | 115.2kbps |
| 功率 - 輸出： | 6dBm |
| 電流 - 傳輸： | 24mA |
| 數(shù)據(jù)接口： | PCB，表面貼裝 |
| 天線連接器： | PCB，表面貼裝 |
| 電源電壓： | 2.2 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
12
Si4022
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
1
0
0
1
1
1
0
fe
0
f5
f4
f3
f2
f1
f0
CE00h
Transmitter FIFO register write
nSEL
SCK
SDI
0
instruction
N data bits
1
2
3
4
5
6
7
filling up FIFO
N-1
N-2
0
1
2
3
4
5
Note
Note
Note
Note
Note:
" If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs t
sx
time, to switch on. The actual value depends on
the type of quartz crystal used.
" If the synthesizer was formerly switched off (es=0), the internal PLL needs t
sp
startup time. Valid data can be transmitted only when the
internal locking process is finished.
Data Transmit Sequence Through the FSK Pin
nSEL
SCK
SDI
instruction
Internal operations
ex, es, etr = 1
xtal osc. stable
Xtal osc staus
FSK
T X D A T A
synthesizer on, PLL locked, PA ready to transmit
synthesizer / PLL /
PA status
tsx *
tsp *
C 0 h
3 8 h
d o n ' t c a r e
P o w e r M a n a g e m e n t c o m m a n d
NOTE:
* See page 5 for the timing values
FIFO Setting Command
Bit 7 <fe>:
Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO.
Bit 5-0 <f5 : f0>:
FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this level.
It is possible to transmit data without the FIFO by using the FSK input pin. In that case the power amplifier should be enabled first with
the Power Management Comand.
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