參數(shù)資料
型號(hào): SI4021-A1-FT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 9/34頁(yè)
文件大?。?/td> 783K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
頻率: 433MHz,868MHz,915MHz
調(diào)制或協(xié)議: FSK,OOK
數(shù)據(jù)傳輸率 - 最大: 512kbps
功率 - 輸出: 8dBm
電流 - 傳輸: 24mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 5.4 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 585 (CN2011-ZH PDF)
其它名稱: 336-1622-5
Si4021
 
 
9
Note 1:   Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period
for sending 100 byte packets in length at 19.2 kbps with +3 dBm output power in the 915 MHz band.
Note 2:   Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency
parameters will change accordingly.
Note 3:   Adjustable in 8 steps.
Note 4:   Optimal antenna admittance/impedance for the Si4021:
 
Yantenna [S]
Zantenna [Ohm]
Lantenna [nH]
434 MHz
1.3E-3 - j6.3E-3
31 + j152
58.00
868 MHz
1.35E-3 - j1.2E-2
9 + j82
15.20
915 MHz
1.45E-3 - j1.3E-2
8.7 + j77
13.60
 
Note 5:   With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration).
Note 6:   During this period, no commands are accepted by the chip. For detailed information see the Reset modes section.
Note 7:   The maximum FSK bitrate and the Output phase noise are dependent on the on the actual setting of the PLL Setting Command.
Note 8:   The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR
crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray
capacitance.
 
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