參數(shù)資料
型號: SI4021-A1-FT
廠商: Silicon Laboratories Inc
文件頁數(shù): 15/34頁
文件大小: 783K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
標準包裝: 96
頻率: 433MHz,868MHz,915MHz
調(diào)制或協(xié)議: FSK,OOK
數(shù)據(jù)傳輸率 - 最大: 512kbps
功率 - 輸出: 8dBm
電流 - 傳輸: 24mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 5.4 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: 336-1622-5
Si4021
 
 
15
3. Frequency Setting Command
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
1
0
1
0     f11    f10     f9
f8
f7
f6
f5
f4
f3
f2
f1
f0
A7D0h
 
The 12-bit parameter of the Frequency Setting Command <f11 : 
f0> has the value F. The value F should be in the range of 96 and 
3903. When F is out of range, the previous value is kept. The
synthesizer center frequency f
0
 can be calculated as:
 
f
0
 = 10 MHz * C1 * (C2 + F/4000)
 
     The constants C1 and C2 are determined by
the selected band as:
Band [MHz]
C1
C2
433
1
43
868
2
43
915
3
30
 
Note:
?    For correct operation of the frequency synthesizer, the frequency and band of operation need to be programmed before the
synthesizer is started. Directly after activation of the synthesizer, the RF VCO is calibrated to ensure proper operation in the
programmed frequency band.
4. Data Rate Command
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
1
1
0
0
1
0
0
0
r7
r6
r5
r4
r3
r2
r1
r0
C800h
In EEPROM mode the transmitted bit rate is determined by the 8-bit value R (bits <r7 : r0>)  as:
 
BR = 10 MHz / 29 / (R+1)
Apart from setting custom values, the standard bit rates from 2.4 to 115.2 kbps can be approximated with minimal error.
The commands are read out with a different fixed bit rate:
 
F
sck
 = 10 MHz / 29 / 3 [~115.2 kHz]
Note:
?    PLL bandwidth should be set according the data rate. Please see the PLL Setting Command.
5. Power Setting Command
bit
7
6
5
4
3
2
1
0
POR
 
1
0
1
1     ook    p2     p1     p0
B0h
The bit ook enables the OOK mode for the PA, in this case the data to be transmitted are received through the FSK pin.
p2    p1    p0   Relative Output Power [dB]
0
0
0
0
0
0
1
-3
0
1
0
-6
0
1
1
-9
1
0
0
-12
1
0
1
-15
1
1
0
-18
1
1
1
-21
 
 
The output power is given in the table as relative to the
maximum available power, which depends on the actual
antenna impedance. (See: Antenna Application Note
available from www.silabs.com/integration).
 
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