參數(shù)資料
型號(hào)： SI4021-A1-FT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 783K
描述： IC TX FSK 915MHZ 5.4V 16-TSSOP
標(biāo)準(zhǔn)包裝： 96
頻率： 433MHz，868MHz，915MHz
調(diào)制或協(xié)議： FSK，OOK
數(shù)據(jù)傳輸率 - 最大： 512kbps
功率 - 輸出： 8dBm
電流 - 傳輸： 24mA
數(shù)據(jù)接口： PCB，表面貼裝
天線連接器： PCB，表面貼裝
電源電壓： 2.2 V ~ 5.4 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 585 (CN2011-ZH PDF)
其它名稱： 336-1622-5
Si4021
 
 
25
RESET MODES 
The chip will enter into reset mode if any of the following conditions are met:
?    Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized
?    Power glitch reset: Transients present on the V
dd
 line
?    Software reset: Special control command received by the chip
Power-on reset
After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which
is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual Vdd and the internal
reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the Vdd voltage is less than 1.6V (typical)
the chip stays in reset mode regardless the voltage difference between the Vdd and the internal ramp signal.
The reset event can last up to 150ms supposing that the V
dd
 reaches 90% its final value within 1ms. During this period the chip does not
accept control commands via the serial control interface.
Power-on reset example:
 
Power glitch reset
The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed
by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection
circuit is disabled.
There can be spikes or glitches on the V
dd
 line if the supply filtering is not satisfactory or the internal resistance of the power supply is too
high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the V
dd
 has a rising
rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the V
dd
 reaches the reset threshold voltage
(600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption
(for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be
disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the Vdd level reaches the reset threshold voltage (250mV in
normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the Vdd must drop below 250mV in order to trigger a power-on reset event
when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will
be generated upon power-up because the power glitch detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.
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