參數(shù)資料
型號: SI4021-A1-FT
廠商: Silicon Laboratories Inc
文件頁數(shù): 21/34頁
文件大?。?/td> 783K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
標準包裝: 96
頻率: 433MHz,868MHz,915MHz
調制或協(xié)議: FSK,OOK
數(shù)據(jù)傳輸率 - 最大: 512kbps
功率 - 輸出: 8dBm
電流 - 傳輸: 24mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 5.4 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: 336-1622-5
Si4021
 
 
21
11. Status Register Read Command
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
- -
With this command, it is possible to read the chips status register through the nIRQ pin. This command clears the last serviced interrupt and
processing the next pending one will start (if there is any).
 
Status Register Read Sequence
nSEL
SCK
SDI
nIRQ
0
instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
POR
PB1
PB2
PB3
PB4
LBD
WK-UP    nIRQ
status out
 
12. PLL Setting and Reset Mode Command
bit     15     14     13     12     11     10
9
8
7
6
5
4
3
2
1
0
POR
 
1
1
0
1
0
0
1
0     bw1   bw0
0
0
0
0
dr
0
D200h
Bits 7-6 <bw1 : bw0> select the PLL bandwidth:
bw1   bw0
Max datarate
[kbps]
Phase Noise at 1MHz offset
[dBc/Hz] (typical)
Charge pump current
0
1
19.2
-112
25%
1
1
38.4
-110
33%
0
0
68.9
-107
50%
1
0
115.2
-102
100%
Bit 1 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
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