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參數(shù)資料
型號(hào)： SI3232PPT0-EVB
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 50/128頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3232
已供物品： 板，CD
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Si3232
28
Preliminary Rev. 0.96
Not
Recommended
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The total power threshold is exceeded (when using
the power calculator method along with the Si3200).
To provide optimal reliability, the device automatically
transitions into the open state until the user changes the
state manually, independent of whether or not the power
alarm interrupt has been masked. The PQ1E to PQ6E
bits of the IRQEN3 register are used to enable the
interrupts for each transistor power alarm, and the
PQ1S to PQ6S bits of the IRQVEC3 register are set
when a power alarm is triggered in the respective
transistor. When using the Si3200, the PQ1E bit is used
to enable the power alarm interrupt, and the PQ1S bit is
set when a Si3200 power alarm is triggered.
4.4.8. Power Dissipation Considerations
The Si3232 relies on the Si3200 to power the line from
the battery supply. The PCB layout and enclosure
conditions should be designed to allow sufficient
thermal
dissipation
out
of
the
Si3200,
and
a
programmable power alarm threshold ensures product
safety under all operating conditions. See “4.4.3. Power
on power alarm considerations. The Si3200’s thermally-
enhanced SOIC-16 package offers an exposed pad that
improves thermal dissipation out of the package when
soldered to a topside PCB pad connected to inner
power planes. Using appropriate layout practices, the
Si3200 can provide thermal performance of 55 °C/W.
The exposed path should be connected to a low-
impedance ground plane via a topside PCB pad directly
under the part. See package outlines for PCB pad
dimensions. In addition, an opposite-side PCB pad with
multiple vias connecting it to the topside pad directly
under the exposed pad further improves the overall
thermal performance of the system. Refer to “AN55:
Dual ProSLIC User Guide” or the Si3232 evaluation
board data sheet for layout guidelines for optimal
thermal dissipation.
Table 16. Register and RAM Locations used for Power Monitoring and Power Fault Detection
Parameter
Location
Register/RAM
Bits
Measurement
Range
Resolution
Si3200 Power Output Monitor
PSUM
PSUM[15:0]
0 to 34.72 W
1059.6
W
Si3200 Power Alarm Interrupt Pending
IRQVEC3
PQ1S
N/A
Si3200 Power Alarm Interrupt Enable
IRQEN3
PQ1E
N/A
Q1/Q2 Power Alarm Threshold (discrete)
Q1/Q2 Power Alarm Threshold (Si3200)
PTH12
PTH12[15:0]
0 to 16.319 W
0 to 34.72 W
498
W
1059.6
W
Q3/Q4 Power Alarm Threshold
PTH34
PTH34[15:0]
0 to 1.03 W
31.4
W
Q5/Q6 Power Alarm Threshold
PTH56
PTH56[15:0]
0 to 16.319 W
498
W
Q1/Q2 Thermal LPF Pole
PLPF12
PLPF12[15:3]
Q3/Q4 Thermal LPF Pole
PLPF34
PLPF34[15:3]
Q5/Q6 Thermal LPF Pole
PLPF56
PLPF56[15:3]
Q1–Q6 Power Alarm Interrupt Pending
IRQVEC3
TBD
N/A
Q71–Q6 Power Alarm Interrupt Enable
IRQEN3
TBD
N/A
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