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參數(shù)資料
| 型號(hào)： | SI3056SSI3-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 32/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SI3056/SI3008 SSI |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，數(shù)據(jù)采集裝置（DAA） |
| 已用 IC / 零件： | Si3056 |
| 已供物品： | 板，CD |
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Si3056
Si3018/19/10
38
Rev. 1.05
provides software control of the secondary frames. As
an alternative method, the FC pin can serve as a
hardware flag for requesting a secondary frame. The
external DSP can turn on the 16-bit TX mode by setting
the SB bit (Register 1, bit 0). In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
cycle and write cycle, respectively. During a read cycle,
the R/W bit is high and the 7-bit address field contains
the address of the register to be read. The contents of
the 8-bit control register are placed on the SDO signal.
During a write cycle, the R/W bit is low and the 7-bit
address field contains the address of the register to be
written. The 8-bit data to be written immediately follows
the address on SDI. Only one register can be read or
written during each secondary frame. See "6.Control
Registers" on page 48 for the register addresses and
functions.
In serial mode 2, the Si3056 operates as a slave device,
where MCLK is an input, SCLK is a no connect, and
FSYNC is an input. In addition, the RGDT/FSD/M1 pin
operates as a delayed frame sync (FSD) and the FC/
RGDT pin operates as ring detect (RGDT). In this
mode, FC operation is not supported. For details on
operating the Si3056 as a slave device, see
5.27. Multiple Device Support
The Si3056 supports the operation of up to seven
additional devices on a single serial interface. Figure 35
shows the typical connection of the Si3056 and one
additional serial voice codec (Si3000).
The Si3056 must be the master in this configuration.
Configure the secondary codec as a slave device with
the master’s SCLK used as the MCLK input to the
codec, and the master’s frame sync delay signal (FSD)
used as the codec’s FSYNC input. On powerup, the
Si3056 master does not detect the additional codec on
the serial bus. The FC/RGDT pin is an input, operating
as the hardware control for secondary frames, and the
RGDT/FSD/M1 pin is an output, operating as the active
low ring detection signal. Program the master device for
master/slave mode before enabling the isolation link,
because a ring signal causes a false transition to the
slave device’s FSYNC.
Register 14 provides the necessary control bits to
configure the Si3056 for master/slave operation. Bit 0
(DCE) sets the Si3056 in master/slave mode, also
referred to as daisy-chain mode. When the DCE bit is
set, the FC/RGDT pin becomes the ring detect output
and the RGDT/FSD/M1 pin becomes the frame sync
delay output. When using multiple devices, secondary
frame communication must be requested via software in
the LSB of the transmit (TX) data word.
Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be
supported on the serial bus. For each slave, the Si3056
generates an FSYNC to the DSP. In daisy-chain mode,
the polarity of the ring signal can be controlled by bit 1
(RPOL). When RPOL = 1, the ring detect signal (now an
output on the FC/RGDT pin) is active high.
The Si3056 supports a variety of codecs and additional
Si3056s. The type of slave codec(s) used is set by the
SSEL[1:0] bits (Register 14, bits 4:3) and determines
the type of signalling used in the LSB of SDO. This
assists the host in isolating which data stream is the
master and which is the slave. If the LSB is used for
signalling, the master device has a unique setting
relative to the slave devices. The DSP can use this
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master Si3056 generates
an FSYNC signal for each device every 16 or 32 SLCK
periods. The delay period is set by FSD (Register 14,
bit 2). Figure 31 on page 43 and Figure 34 on page 46
show the relative timing for daisy chaining operation.
Primary communication frames occur in sequence,
followed by secondary communication frames, if
requested. When writing/reading the master device via
a secondary frame, all secondary frames of the slave
devices also must be written. When writing/reading a
slave device via a secondary frame, the secondary
frames of the master and all other slaves must be
written also. “No operation” writes/reads to secondary
frames are accomplished by writing/reading a 0 value to
address 0.
If FSD is set for 16 SCLK periods between FSYNCs,
only serial mode 1 can be used. In addition, the slave
devices must delay the tri-state to active transition of
their SDO sufficiently from the rising edge of SCLK to
avoid bus contention.
The Si3056 supports the operation of up to eight Si3056
devices on a single serial bus. The master Si3056 must
be configured in serial mode 1. Configure the slave(s)
Si3056 in serial mode 2. Figure 36 on page 47 shows a
typical master/slave connection using three Si3056
devices.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD/M1 becomes the delay frame sync output,
and FC/RGDT becomes the ring detection output. The
serial interface runs at the MCLK input frequency fed
from a master device (such as a master Si3056's SCLK
output). To achieve the proper sampling frequency, the
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