參數(shù)資料
型號(hào)： SI3056SSI3-EVB
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 30/94頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL SI3056/SI3008 SSI
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，數(shù)據(jù)采集裝置（DAA）
已用 IC / 零件： Si3056
已供物品： 板，CD
Si3056
Si3018/19/10
36
Rev. 1.05
5.24. Filter Selection
The Si3056 supports additional filter selections for the
receive and transmit signals as defined in Table 11 and
Table 12 on page 15. The IIRE bit (Register 16, bit 4)
selects between the IIR and FIR filters. The IIR filter
provides a shorter, but non-linear, group delay
alternative to the default FIR filter and only operates
with an 8 kHz sample rate. Also, on the Si3019 line-side
device, the FILT bit (Register 31, bit 1) selects a –3 dB
low frequency pole of 5 Hz when cleared and 200 Hz
when set. The FILT bit affects the receive path only.
5.25. Clock Generation
The Si3056 has an on-chip clock generator. Using a
single MCLK input frequency, the Si3056 generates all
the desired standard modem sample rates.
The clock generator consists of two phase-locked loops
(PLL1 and PLL2) that achieve the desired sample
frequencies. Figure 26 illustrates the clock generator.
The architecture of the dual PLL scheme provides fast
lock time on initial start-up, fast lock time when
changing modem sample rates, high noise immunity,
and can change modem sample rates with a single
register write. Many MCLK frequencies between
1 and 60 MHz are supported. MCLK should be from a
clean source, preferably directly from a crystal with a
constant frequency and no dropped pulses.
In serial mode 2 (refer to the “5.26.Digital Interface”
section), the Si3056 operates as a slave device. The
clock generator is configured based on the SRC register
to generate the required internal clock frequencies. In
this mode, PLL2 is powered-down. For further details of
slave mode operation, see "5.27.Multiple Device
5.25.1. Programming the Clock Generator
As shown in Figure 26, PLL1 must output a clock equal
to 98.304 MHz (FBASE). The FBASE is determined by
programming the following registers:
Register 8: PLL1 N[7:0] divider.
Register 9: PLL1 M[7:0] divider.
The main design consideration is the generation of a
base frequency, defined as follows:
N (Register 8) and M (Register 9) are 8-bit unsigned
values. FMCLK is the frequency of the clock provided to
the MCLK pin.
Table 20 lists several standard crystal oscillator rates
that can be supplied to MCLK. This list represents a
sample of MCLK frequency choices. Many others are
possible.
After PLL1 is programmed, the SRC[3:0] bits can
achieve the standard modem sampling rates with a
single write to Register 7. See "Register 7.Sample Rate
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N (Register 8, bits 7:0) must be written first,
then immediately followed by a write to M (Register 9,
bits 7:0).
The values shown in Table 20 satisfy the preceding
equation. However, when programming the registers for
N and M, the value placed in these registers must be
one less than the value calculated from the equations.
For example, with an MCLK of 46.08 MHz, the values
placed in the N and M registers are 0x0Dh and 0x1Fh,
respectively.
FBASE
FMCLK M
×
N
-----------------------------
98.304 MHz
==
Table 20. MCLK Examples
MCLK (MHz)
N
M
1.8432
3
160
4.0960
1
24
6.1440
1
16
8.1920
1
12
9.2160
3
32
10.3680
27
256
11.0592
9
80
12.288
1
8
14.7456
3
20
18.4320
3
16
24.5760
1
4
25.8048
21
80
44.2368
9
20
46.0800
15
32
47.9232
39
80
56.0000
35
36
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