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參數(shù)資料
| 型號： | SI3056DC1-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 47/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTERCARD DAA SI3056/SI3019 |
| 標準包裝： | 1 |
| 主要目的： | 電信，數(shù)據(jù)采集裝置（DAA） |
| 已用 IC / 零件： | Si3056 |
| 已供物品： | 板，CD |
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Si3056
Si3018/19/10
Rev. 1.05
51
Reset settings = 0000_0000
Register 3. Interrupt Mask
Bit
D7D6D5
D4D3
D2
D1
D0
Name
RDTM ROVM FDTM
BTDM DODM LCSOM DLCSM
POLM
Type
R/W
Bit
Name
Function
7RDTM
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
6ROVM
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
5FDTM
Frame Detect Mask.
0 = The communications link achieving frame lock does not cause an interrupt on the AOUT/
INT pin.
1 = The communications link achieving frame lock causes an interrupt on the AOUT/INT pin.
4BTDM
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
3DODM
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
2LCSOM
Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
1DLCSM
Delta Loop Current Sense Mask.
0 = An interrupt does not occur when the LCS bits change.
1 = An interrupt does occur when the LCS bits change.
0POLM
Polarity Reversal Detect Mask.
Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity
of TIP and RING was switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
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