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參數(shù)資料
| 型號(hào)： | SI3050-E1-GM |
| 廠(chǎng)商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 57/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC VOICE DAA SYSTEM SIDE 24QFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | * |
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Si3050 + Si3011/18/19
34
Rev. 1.5
5.19. Ring Validation
Ring validation prevents false triggering of a ring
detection by validating the ring parameters. Invalid
signals, such as a line-voltage change when a parallel
handset goes off-hook, pulse dialing, or a high-voltage
line test are ignored. Ring validation can be enabled
during normal operation and in low-power sleep mode
when a valid external PCLK signal is supplied.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
Ring validation requires the following five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal (the RAS[5:0] bits in
Register 24). The frequency is measured by
calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency (the RMX[5:0] bits in Register 22).
Time interval over which the ring signal must be the
correct frequency (the RCC[2:0] bits in Register 23).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
accommodate distinctive ringing.
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in both normal operating
mode and low-power sleep mode.
Ring validation affects the behavior of the RDT status
bit, the RDTI interrupt, the INT pin, and the RGDT pin.
1. When ring validation is enabled, the status bit seen
in the RDT read-only bit (r5.2), represents the
detected envelope of the ring. The ring validation
parameters are configurable so that this envelope
may remain high throughout a distinctive-ring
sequence.
2. The RDTI interrupt fires when a validated ring
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
3. The INT pin follows the RDTI bit with configurable
polarity.
4. The RGDT pin can be configured to follow the
ringing signal envelope detected by the ring
validation circuit by setting RFWE to 0. If RFWE is
set to 1, the RGDT pin follows an unqualified ring
detect one-shot signal initiated by a ring-threshold
crossing and terminated by a fixed counter timeout
of approximately 5 seconds. (This information is
shown in Register 18).
5.20. Ringer Impedance and Threshold
The ring detector in a typical DAA is ac coupled to the
line with a large 1
F, 250 V decoupling capacitor. The
ring detector on the Si3011/18/19 is resistively coupled
to the line. This coupling produces a high ringer
impedance to the line of approximately 20 M
to meet
the majority of country PTT specifications including FCC
and TBR21.
Several countries including Poland, South Africa, and
Slovenia require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit (Register 16). Certain countries also
specify ringer thresholds differently. The RT and RT2
bits (Register 16 and Register 17, respectively) select
between three different ringer thresholds: 15 V ±10%,
21 V ±10%, and 45 V ±10%. These three settings
enable
satisfaction
of
global
ringer
threshold
requirements. Thresholds are set so that a ring signal is
guaranteed to not be detected below the minimum, and
a ring signal is guaranteed to be detected above the
maximum.
5.21. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
The Si3050 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
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| SI3050-E1-GMR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - LEAD-FREE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 24QFN 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
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| SI3050-E1-GTR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 24QFN 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
| Si3050-E-FM | 功能描述:電信語(yǔ)音調(diào)制 IC Si3050 Voice DAA System-Side RoHS:否 制造商:Epson Electronics America 產(chǎn)品: 應(yīng)用:Voice Guidance product 封裝 / 箱體:PQFP-52 電源電壓-最大:3.6 V, 5.5 V 最大工作溫度: 最小工作溫度: 封裝: |
| SI3050-E-FMR | 功能描述:電信線(xiàn)路管理 IC Si3050 Voice DAA System-Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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