參數(shù)資料
型號: SI3050-E1-FM
廠商: Silicon Laboratories Inc
文件頁數(shù): 89/128頁
文件大?。?/td> 0K
描述: IC VOICE DAA SYSTEM SIDE 24QFN
標準包裝: 75
系列: *
Si3050 + Si3011/18/19
Rev. 1.5
63
Reset settings = 0000_0000
Register 1. Control 1
Bit
D7D6D5D4D3D2
D1
D0
Name
SR
PWMM[1:0]
PWME
IDL
Type
R/W
Bit
Name
Function
7SR
Software Reset.
0 = Enables the DAA for normal operation.
1 = Sets all registers to their reset value.
Note:
Bit automatically clears after being set.
6
Reserved
Read returns zero.
5:4
PWMM[1:0]
Pulse Width Modulation Mode.
Used to select the type of signal output on the call progress AOUT pin.
00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of
1s and 0s tracks the combined transmit and receive signals. Use this setting with the optional
call progress circuit shown in Figure 19 on page 20.
01 = Balanced conventional PWM output signal has high and low portions of the modulated
pulse that are centered on the 16 kHz sample clock.
10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises
at a time in the 32 kHz period proportional to its instantaneous amplitude.
11 = Reserved.
3
PWME
Pulse Width Modulation Enable.
0 = Pulse width modulation mode disabled (AOUT).
1 = Enable pulse width modulation mode for the call progress analog output (AOUT). This
mode sums the transmit and receive audio paths and presents this as a CMOS digital-level
output of PWM data. The circuit in Figure 19 on page 20 should be used.
2
Reserved
Read returns zero.
1IDL
Isolation Digital Loopback.
0 = Digital loopback across the isolation barrier is disabled.
1 = Enables digital loopback mode across the isolation barrier. The line-side device must be
enabled and off-hook prior to setting this mode. The data path includes the TX and RX filters.
0
Reserved
Read returns zero.
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