參數(shù)資料
型號: SI3050-E1-FM
廠商: Silicon Laboratories Inc
文件頁數(shù): 103/128頁
文件大小: 0K
描述: IC VOICE DAA SYSTEM SIDE 24QFN
標(biāo)準(zhǔn)包裝: 75
系列: *
Si3050 + Si3011/18/19
76
Rev. 1.5
Reset settings = 0000_0000
1ROV
Receive Overload.
This bit is set when the receive input has an excessive input level (i.e., receive pin goes below
ground). Writing a 0 to this location clears this bit and the ROVI bit (Register 4, bit 6).
0 = Normal receive input level.
1 = Excessive receive input level.
0BTD
Billing Tone Detected.
This bit is set if an event, such as a billing tone, causes a disruption in the line-side power
supply. Writing a zero to BTE clears this bit.
0 = No billing tone detected.
1 = Billing tone detected.
Register 18. International Control 3
Bit
D7D6D5D4D3D2D1D0
Name
RFWE
Type
R/W
Bit
Name
Function
7:3
Reserved Read returns zero.
2
Reserved This bit may be written to a zero or one.
1RFWE
Ring Detector Full-Wave Rectifier Enable.
When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser-
tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow
the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect
one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout
of approximately 5 seconds.
RNGV
RFWE
RGDT
0
Half-Wave
0
1
Full-Wave
1
0
Validated Ring Envelope
1
Ring Threshold Crossing One-Shot
0
Reserved Read returns zero.
Bit
Name
Function
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