參數(shù)資料
型號(hào): SI3016-F-FS
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/50頁
文件大?。?/td> 0K
描述: IC LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝: 48
數(shù)據(jù)格式: V.90
電源電壓: 3.3V,5V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 管件
Si3016
14
Rev. 1.0
4.1. Initialization
When the integrated system-side module and the
Si3016 are initially powered up, the DAA registers will
have default values that guarantee the line-side chip
(Si3016) is powered down with no possibility of loading
the line (i.e., off-hook). An example initialization
procedure is outlined below:
1. Program the desired sample rate with the Sample
Rate Control Register.
2. Wait until the Si3016 PLL is locked. This time is
between 100 s and 1 ms.
3. Write a 00H into the DAA Control 2 Register. This
powers up the line-side chip (Si3016) and enables
the AOUT for call progress monitoring.
4. Set the desired line interface parameters (i.e.,
DCT[1:0], ACT, OHS, RT, LIM[1:0], and VOL) as
defined by “Country Specific Register Settings”
After this procedure is complete, the Si3016 is ready for
ring detection and off-hook.
4.2. Power Supply
When on-hook, the Si3016 draws power across the
isolation link from the system-side module. When off-
hook, power is drawn from the 2-wire line. Thus, no
power supply connections are needed for the Si3016.
4.3. Isolation Barrier
The Si3016 achieves an isolation barrier through low-
cost, high-voltage capacitors in conjunction with Silicon
Laboratories’ proprietary signal processing techniques.
These techniques eliminate any signal degradation due
to capacitor mismatches, common mode interference, or
noise coupling. As shown in Figure 6 on page 9, the C1,
C4, C24, and C25 capacitors isolate the system side
from the Si3016 (line side). All transmit, receive, control,
ring detect, and caller ID data are communicated through
this barrier.
The isolated communications link is disabled by default.
To enable it, the PDL bit must be cleared. No
communication between the system-side module and
the Si3016 can occur until this bit is cleared. When the
PDL bit is cleared, a check is performed to ensure that
the line-side device is an Si3016 device. If it is not, the
system-side module will not function.
4.4. Transmit/Receive Full Scale Level
The Si3016 supports programmable maximum transmit
and receive levels. The full-scale TX/RX level is
established by writing the FULL bit in Register 18. With
FULL = 1, the full scale TX/RX level is increased to
3.2 dBm to support certain FCC voice applications that
require higher TX/RX levels. When FULL = 1, R2 must
be changed from 402
Ω to 243 Ω. The default full scale
value is –1 dBm (FULL = 0). Note that this higher TX/
RX full-scale mode must be used in FCC/600
Ω
termination mode.
Spain
0
0 or 1
11
0
1
0
Sweden
0
0 or 1
11
0
1
0
Switzerland
0
0 or 1
11
0
1
0
Syria1
00
01
00
0
Taiwan1
00
01
00
0
Thailand1
00
01
00
0
UAE
0
0100
0
United Kingdom
0
0 or 1
11
0
1
0
USA
0
0100
0
Yemen
0
0100
0
Table 9. Country Specific Register Settings
Register
16
17
18
Country
OHS
ACT
DCT[1:0]
RZ
RT
LIM
VOL
Notes:
1. See "4.9. DC Termination Considerations" on page 17 for more information.
2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
3. Supported for loop current
≥ 20 mA.
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