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| 型號： | SI3016-F-FS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 數(shù)據(jù)格式： | V.90 |
| 電源電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3016
24
Rev. 1.0
4.25. In-Circuit Testing
The Si3016’s advanced design provides the designer
with
an
increased
ability
to
determine
system
functionality during production line tests, as well as
support for end-user diagnostics. Four loopback modes
exist
allowing
increased
coverage
of
system
components. For three of the test modes, a line-side
power source is needed. While a standard phone line
can be used, the test circuit in Figure 1 on page 5 is
adequate. In addition, an off-hook sequence must be
performed to connect the power source to the line-side
chip.
For the startup test mode, no line-side power is
necessary and no off-hook sequence is required. The
startup test mode is enabled by default. When the PDL
bit is set (the default case), the line side is in a power-
down mode and the system-side module is in a digital
loop-back mode. In this mode, data received on SDI is
passed through the internal filters and transmitted on
SDO. This path will introduce approximately 0.9 dB of
attenuation on the SDI signal received. The group delay
of both transmit and receive filters will exist between
SDI and SDO. Clearing the PDL bit disables this mode,
and the SDO data is switched to the receive data from
the line-side. When the PDL bit is cleared, the FDT bit
becomes active, indicating successful communication
between the line-side and DSP-side. This can be used
to verify that the isolation link is operational.
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
requirements:
1. Powerup or reset.
2. Program the desired sample rate.
3. Enable the line side by clearing the PDL bit.
4. Issue off-hook
5. Delay 1548/Fs sec to allow calibration to occur.
6. Set the desired test mode.
The isolation link digital loopback mode allows the data
pump to provide a digital input test pattern on the
system-side module and receive that digital test pattern
back on the system-side module. To enable this mode,
set the DL bit. In this mode, the isolation barrier is
actually being tested. The digital stream is delivered
across the isolation capacitor, C1, of Figure 6 on page 9
to the line side device and returned across the same
barrier. Note that in this mode, the 0.9 dB attenuation
and filter group delays also exist.
The analog loopback mode allows an external device to
drive a signal on the telephone line into the Si3016 line-
side device and have it driven back out onto the line.
This mode allows testing of external components
connecting the RJ-11 jack (TIP and RING) to the
Si3016. To enable this mode, set the AL bit.
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the transmit
and receive paths on the line-side chip and the external
components in Figure 6 on page 9. In this test mode,
the data pump provides a digital test waveform on the
system-side module. This data is passed across the
isolation barrier, transmitted to and received from the
line, passed back across the isolation barrier, and
presented back to the data pump from the system-side
module. To enable this mode, clear the HBE bit.
When the HBE bit is cleared, this will cause a dc offset
which affects the signal swing of the transmit signal. In
this test mode, it is recommended that the transmit
signal be 12 dB lower than normal transmit levels. This
lower level will eliminate clipping caused by the dc offset
which results from disabling the hybrid. It is assumed in
this test that the line ac impedance is nominally 600
Ω.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
4.26. Exception Handling
The Si3016 provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling DSP
can read several status bits. The bit of highest
importance is the frame detect bit FDT. This bit indicates
that the system-side module and line-side (Si3016)
device are communicating. During normal operation,
the FDT bit can be checked before reading any bits that
indicate information about the line side. If FDT is not
set, the following bits related to the line side are invalid:
RDT,
RDTN,
RDTP,
LCS[3:0],
CBID,
REVB[3:0],
LVCS[4:0], ROV, BTD, DOD, OPD, and OVL.
Following powerup and reset, the FDT bit is not set
because the PDL bit defaults to 1. In this state, the link
is not operating, and no information about the line side
can be determined. The user must program the desired
sample rate and clear the PDL bit to activate the link.
While the system and line side are establishing
communication, the system-side does not generate
FSYNC signals. Establishing communication will take
less than 10 ms.
The FDT bit can also indicate if the line side executes
an off-hook request successfully. If the line side is not
connected to a phone line (i.e., the user fails to connect
a phone line to the modem), the FDT bit remains
cleared. The controlling processor must allow sufficient
time for the line side to execute the off-hook request.
The maximum time for FDT to be valid following an off-
hook request is 10 ms. If the FDT bit is high, the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3016-F-FSR | 功能描述:電信線路管理 IC Line-Side device Processor Integrated RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3016-F-KS | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3016-F-KSR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3016-FS | 功能描述:IC LINE-SIDE DAA 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 調(diào)制解調(diào)器 - IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 數(shù)據(jù)格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應(yīng)商設(shè)備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
| SI3016-FSR | 功能描述:IC LINE-SIDE DAA 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 調(diào)制解調(diào)器 - IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 數(shù)據(jù)格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應(yīng)商設(shè)備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
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