- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373394 > SI3014-KS (Electronic Theatre Controls, Inc.) 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT PDF資料下載
參數(shù)資料
| 型號(hào)： | SI3014-KS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| 中文描述： | 3.3伏催化裂化/ JATE直接訪問安排 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | SI3014-KS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Si3035
26
Rev. 1.2
signalling, the master device will have a unique setting
relative to the slave devices. The DSP can use this
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master Si3035 will
generate an FSYNC signal for each device every 16 or
32 SCLK periods. The delay period is set by Register 14,
bit 2 (FSD). Figures 26–29 show the relative timing for
daisy chaining operation. Primary communication
frames occur in sequence, followed by secondary
communication
frames,
writing/reading the master device via a secondary frame,
all secondary frames of the slave devices must be
written as well. When writing/reading a slave device via
a secondary frame, the secondary frames of the master
and all other slaves must be written as well. "No
operation" writes/reads to secondary frames are
accomplished by writing/reading a zero value to address
zero.
If FSD is set for 16 SCLK periods between FSYNCs,
only serial mode 1 can be used. In addition, the slave
devices must delay the tri-state to active transition of
their SDO sufficiently from the rising edge of SCLK to
avoid bus contention.
The Si3035 supports the operation of up to eight Si3035
devices on a single serial bus. The master Si3035 must
be configured in serial mode 1. The slave(s) Si3035 is
configured in serial mode 2. Figure 30 shows a typical
master/slave connection using three Si3035 devices.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD becomes the delay frame sync output, and
FC/RGDT becomes the ring detection output. In
addition, the internal PLLs are fixed to a multiply by 20.
This provides the desired sample rate when the master’s
SCLK is provided to the slave’s MCLK. The SCLK of the
slave is a no connect in this configuration. The delay
between FSYNC input and delayed frame sync output
(RGDT/FSD) will be 16 SCLK periods. The RGDT/FSD
output has a waveform identical to the FSYNC signal in
serial mode 0. In addition, the LSB of SDO is set to zero
by default for all devices in serial mode 2.
Gain Control
The Si3035 supports multiple gain and attenuation
settings for the receive and transmit paths, respectively,
via Register 13. When the ARX bit is set, 6 dB of gain is
applied to the receive path. When the ATX bit is set,
–3 dB of gain is applied to the transmit path.
Register 15 can be used to provide additional gain
control. For Register 15 to have an effect on the receive
and transmit paths, the ATX and ARX bits of
if
requested.
When
Register 13 must be 0.
The receive path can support gains of 0, 3, 6, 9, and
12 dB. The gain is selected by bits 2:0 (ARX2:ARX0).
The receive path can also be muted by setting bit 3
(RXM). The transmit path can support attenuations of 0,
3, 6, 9, and 12 dB. The attenuation is selected by bits
6:4 (ATX2:ATX0). The transmit path can also be muted
by setting bit 7 (TXM).
Filter Selection
The Si3035 supports additional filter selections for the
receive and transmit signals. When set, the IIRE bit of
Register 16 enables the IIR filters defined in Table 12 on
page 11. This filter provides a much lower, however
non-linear, group delay than the default FIR filters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI3014-KT | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3015-BS | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3015-KS | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3021 | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3021-BS | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3014-KSR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3014-KT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL MC 97 SILICON DAA |
| SI3015 | 制造商:SILABS 制造商全稱:SILABS 功能描述:V.22BIS ISOMODEM CHIPSET WITH ERROR CORRECTION |
| SI3015-BS | 功能描述:電信線路管理 IC CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3015-BSR | 功能描述:電信線路管理 IC CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。