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參數(shù)資料
| 型號： | SCF5250VM120 |
| 廠商： | Motorola, Inc. |
| 英文描述： | SCF5250 Integrated ColdFire Microprocessor |
| 中文描述： | SCF5250提供了集成的ColdFire微處理器 |
| 文件頁數(shù)： | 32/48頁 |
| 文件大?。?/td> | 767K |
| 代理商： | SCF5250VM120 |
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SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Electrical Characteristics
Freescale Semiconductor
32
Table 25. I2C-Bus Input Timing Specifications Between SCL and SDA
Num
Characteristic
Units
Min
Max
M1
Start Condition Hold Time
2
—
bus clocks
M2
Clock Low Period
8
—
bus clocks
M3
SCL/SDA Rise Time
(VIL= 0.5 V to VIH = 2.4 V)
—
1
mSec
M4
Data Hold Time
0
—
nSec
M5
SCL/SDA Fall Time
(VIH= 2.4 V to VIL = 0.5 V)
—
1
mSec
M6
Clock High time
4
—
bus clocks
M7
Data Setup Time
0
—
nSec
M8
Start Condition Setup Time
(for repeated start condition only)
2
—
bus clocks
M9
Stop Condition Setup Time
2
—
bus clocks
Table 26. I2C-Bus Output Timing Specifications Between SCL and SDA
Num
Characteristic
Units
Min
Max
M1
1
Start Condition Hold Time
6
—
bus clocks
M2
1
Clock Low Period
10
—
bus clocks
M3
2
SCL/SDA Rise Time
(V
IL
= 0.5 V to V
IH
= 2.4 V)
note 2
note 2
mSec
M4
1
Data Hold Time
7
—
bus clocks
M5
3
SCL/SDA Fall Time
(V
IH
= 2.4 V to V
IL
= 0.5 V)
—
3
nSec
M6
1
Clock High time
10
—
bus clocks
M7
1
Data Setup Time
2
—
bus clocks
M8
1
Start Condition Setup Time
(for repeated start condition only)
20
—
bus clocks
M9
1
Stop Condition Setup Time
10
—
bus clocks
1.
Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed
with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above
table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of
the SCL low period. The actual position is affected by the prescale and division values programmed into
the MFDR; however, numbers given in the above table are the minimum values.
2.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the
time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up
resistor values.
3.
Specified at a nominal 20 pF load.
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