參數(shù)資料
型號(hào): SCF5250VM120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁(yè)數(shù): 12/48頁(yè)
文件大?。?/td> 767K
代理商: SCF5250VM120
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Signal Descriptions
Freescale Semiconductor
12
4.2
GPIO
Many pins have an optional GPIO function.
General purpose input is always active, regardless of state of pin.
General purpose output or primary output is determined by the appropriate setting of the Pin
Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.
At Power-on reset, all pins are set to their primary function.
4.3
SCF5250 Bus Signals
These signals provide the external bus interface to the SCF5250.
Linear regulator input
LININ
Input, typically I/O supply (3.3V)
In
Linear regulator ground
LINGND
High Impedance
HI-Z
Assertion Tri-states all output signal
pins.
In
Debug Data
DDATA0/CTS1/SDATA0_SDIO1/GPIO1
DDATA1/RTS1/SDATA2_BS2/GPIO2
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
Displays captured processor data and
break-point status.
In/Out
Hi-Z
Processor Status
PST0/GPIO50
PST1/GPIO49
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
Indicates internal processor status.
In/Out
Hi-Z
Processor clock
PSTCLK/GPIO51
processor clock output
Out
Test Clock
TCK
Clock signal for IEEE 1149.1A JTAG.
In
Test Reset/Development
Serial Clock
TRST/DSCLK
Multiplexed signal that is
asynchronous reset for JTAG
controller. Clock input for debug
module.
In
Test Mode Select/ Break
Point
TMS/BKPT
Multiplexed signal that is test mode
select in JTAG mode and a hardware
break-point in debug mode.
In
Test Data Input /
Development Serial Input
TDI/DSI
Multiplexed serial input for the JTAG or
background debug module.
In
Test Data
Output/Development Serial
Output
TDO/DSO
Multiplexed serial output for the JTAG
or background debug module.
Out
Table 3. SCF5250 Signal Index (continued)
Signal Name
Mnemonic
Function
Input/
Output
Reset
State
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