參數(shù)資料
型號(hào): SCF5250VM120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁數(shù): 26/48頁
文件大小: 767K
代理商: SCF5250VM120
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Electrical Characteristics
Freescale Semiconductor
26
Table 20. Input AC Timing Specification
Num
Characteristic
Units
Min
Max
B1
1,2
Signal Valid to BCLK Rising (setup)
3
nSec
B2
1
BCLK Rising to signal Invalid (hold)
2
nSec
B3
1
BCLK to Input High Impedance
5
BCLK
cycle
1.
2.
Inputs (rising): DATA[31:16]
AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on
output pins. If this value is different, the input and output timing specifications would need to
be adjusted to match the clock load.
Table 21. Output AC Timing Specification
Num
Characteristic
5
Units
Min
Max
B10
1
BCLK (8mA) Rising to signal Valid
---
10
nSec
B11
1
BCLK (8mA) Rising to signal Invalid (hold)
3.5
nSec
B10
2
BCLK (4mA) Rising to signal Valid
---
11
nSec
B11
2
BCLK (4mA) Rising to signal Invalid (hold)
4
nSec
B12
3
BCLK to High Impedance
(Three-State)
---
14
nSec
H1
HIZ to High Impedance
tbd
nSec
H2
HIZ to Low Impedance
tbd
nSec
1.
Outputs (8mA): DATA[31:16], ADDR[25,23:9]
2.
Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE
3.
High Impedance (Three-State): DATA[31:16]
4.
AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output
pins. If this value is different, the input and output timing specifications would need to be adjusted
to match the clock load.
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