SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Se" />
參數(shù)資料
型號(hào)： SCF5250CAG120
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 25/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU COLDFIRE 120MHZ 144-QFP
標(biāo)準(zhǔn)包裝： 60
系列： SCF52xx
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 120MHz
連通性： EBI/EMI，I²C，IDE，MMC，SPI，UART/USART
外圍設(shè)備： DMA，I²S，POR，串行音頻，WDT
輸入/輸出數(shù)： 57
程序存儲(chǔ)器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
31
Figure 8 provides the I2C-bus input and output timing diagram and Table 26 and Table 27 provide the
I2C-bus input and output timing parameters.
Figure 8. I2C-Bus Input/Output Timing Definition Diagram
Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA
Num
Characteristic
Min
Max
Units
M1
Start Condition Hold Time
2
–
bus clocks
M2
Clock Low Period
8
–
bus clocks
M3
SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V)
–
1
mSec
M4
Data Hold Time
0
–
ns
M5
SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V)
–
1
ms
M6
Clock High time
4
–
bus clocks
M7
Data Setup Time
0
–
ns
M8
Start Condition Setup Time (for repeated start condition only)
2
–
bus clocks
M9
Stop Condition Setup Time
2
–
bus clocks
Table 27. I2C-Bus Output Timing Specifications Between SCL and SDA
Num
Characteristic
Min
Max
Units
M11
1 Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed with the maximum frequency (MFDR =
0x20) will result in minimum output timings as shown. The MBUS interface is designed to scale the actual data transition time to move it to
the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the MFDR; however,
numbers given are the minimum values.
Start Condition Hold Time
6
–
bus clocks
M21
Clock Low Period
10
–
bus clocks
M32
2 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to
reach a high level depends on external signal capacitance and pull-up resistor values.
SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V)
note 2
mSec
M41
Data Hold Time
7
–
bus clocks
M53
3 Specified at a nominal 20 pF load.
SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V)
–3
ns
M61
Clock High time
10
–
bus clocks
M71
Data Setup Time
2
–
bus clocks
M81
Start Condition Setup Time (for repeated start condition only)
20
–
bus clocks
M91
Stop Condition Setup Time
10
–
bus clocks
M2
M6
M1
M4
M7
M8
M9
M5
M3
SCL
SDA
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