參數(shù)資料
型號(hào): SCANSTA111SM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: EMITTER IR 850NM 5MM RADIAL
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49
封裝: BGA-49
文件頁(yè)數(shù): 4/29頁(yè)
文件大?。?/td> 524K
代理商: SCANSTA111SM
TABLE 2. Pin Descriptions
Pin Name
VCC
GND
TMS
B
Description
No.
Pins
3
3
1
I/O
N/A
N/A
I
Power
Ground
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
’STA111. Also controls sequencing of the TAPs which are on the local scan chains. This input
has a 25K
pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate
method). When the device is power-off (V
DD
floating), this input appears to be a capacitive
load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears
to be a capacitive load with the pull-up to ground.
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA111 through
this input pin. This input has a 25K
pull-up resistor and no ESD clamp diode (ESD is
controlled with an alternate method). When the device is power-off (V
DD
floating), this input
appears to be a capacitive load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied
to V
SS
) this input appears to be a capacitive load with the pull-up to ground.
BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA111 and the
local TAPs, back toward the scan master controller. This output has 24mA of drive current.
When the device is power-off (V
DD
= 0V or floating), this output appears to be a capacitive
load (Note 4).
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the ’STA111 and of the local scan ports. This input has no pull-up
resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the
device is power-off (V
DD
floating), this input appears to be a capacitive load to ground (Note
4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to be a capacitive
load to ground.
TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA111 logic.
This input has a 25K
pull-up resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
DD
floating), this input appears to be a
capacitive load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this
input appears to be a capacitive load with the pull-up to ground.
BACKPLANE TRI-STATE NOTIFICATION OUTPUT: This signal is high when the backplane
scan port is TRI-STATEd. This pin is used for backplane physical layer changes (i.e.; TTL to
LVDS). This output has 12mA of drive current.
BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y
n
of
a single selected LSP. (Not available when multiple LSPs are selected). This input has an
internal pull-up resistor.
BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the
A
n
of a single selected LSP. (Not available when multiple LSPs are selected). This output
has 24mA of drive current.
SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique
address to) each ’STA111 on the system backplane (Note 1).
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control
signal TRI-STATEs all local scan ports on the ’STA111, to enable an alternate resource to
access one or more of the three local scan chains.
TEST DATA OUTPUTS: Individual output for each of the local scan ports (Note 2). These
outputs have 24mA of drive current.
TEST DATA INPUTS: Individual scan data input for each of the local scan ports (Note 2).
TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS
n
does not provide a pull-up resistor (which is assumed to be present on a connected TMS
input, per the IEEE 1149.1 requirement) (Note 2). These outputs have 24mA of drive current.
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These
are buffered versions of TCK
B
(Note 2). These outputs have 24mA of drive current.
TDI
B
1
I
TDO
B
1
O
TCK
B
1
I
TRST
B
1
I
TRIST
B
1
O
A
B
1
I
Y
B
1
O
S
(0-6)
7
I
OE
1
I
TDO
(0-2)
3
O
TDI
(0-2)
TMS
(0-2)
3
3
I
O
TCK
(0-2)
3
O
S
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