參數(shù)資料
型號: SCANSTA111SM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: EMITTER IR 850NM 5MM RADIAL
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49
封裝: BGA-49
文件頁數(shù): 18/29頁
文件大小: 524K
代理商: SCANSTA111SM
Register Descriptions
(Continued)
count (zero). It is cleared (logic 0) when the counter is loaded
following a
CNTRSEL
instruction. The power-on value for bit
7 is 0.
Bits 5 and 6 are optional in the HDL to support five LSPs with
a single Mode Register
. A second Mode Register
1
may be
added to allow support of up to eight LSPs.
TABLE 9. Mode Register
0
BIT
Description
Used in Silicon Y
Default Value
7
TCK Counter Status LSP
4
LSP
3
TDI
B
to TDO
B
Loopback TCK Free Running Disable LSP
2
LSP
1
LSP
0
N
N
Y
0
0
0
0
6
5
4
3
2
1
0
Y
0
Y
0
Y
0
Y
1
TABLE 10. Mode Register
1
BIT
Description
Used in Silicon
Default Value
7
Reserved
N
0
6
Reserved
N
0
5
Reserved
N
0
4
Reserved
N
0
3
Reserved
N
0
2
LSP
7
N
0
1
LSP
6
N
0
0
LSP
5
N
0
TABLE 11. Mode Register
2
BIT
Description
Used in Silicon N
Default Value
7
LSP
7
/GPIO
7
LSP
6
/GPIO
6
LSP
5
/GPIO
5
LSP
4
/GPIO
4
LSP
3
/GPIO
3
LSP
2
/GPIO
2
LSP
1
/GPIO
1
LSP
0
/GPIO
0
N
N
N
0
0
0
0
6
5
4
3
2
1
0
N
0
Y
0
Y
0
Y
0
DEVICE IDENTIFICATION REGISTER:
The device identifi-
cation register (IDREG) is a 32-bit register compliant with
IEEE Std. 1149.1. When the
IDCODE
instruction is active,
the identification register is loaded with the Hex value upon
leaving the
Capture-DR
state (on the rising edge of the
TCK
). Refer to the currently available BSDL file on our
website for the most accurate Device ID.
LINEAR FEEDBACK SHIFT REGISTER:
The ’STA111 con-
tains a signature compactor which supports test result evalu-
ation in a multi-chain environment. The signature compactor
consists of a 16-bit linear-feedback shift register (LFSR)
which can monitor local-port scan data as it is shifted up-
stream from the ’STA111’s local-port network. Once the
LFSR is enabled, the LFSR’s state changes in a reproduc-
ible way as each local-port data bit is shifted in from the
local-port network. When all local-port data has been
scanned in, the LFSR contains a 16-bit signature value
which can be compared against a signature computed for
the expected results vector.
The LFSR uses the following feedback polynomial:
F(x) = X
16
+ X
12
+ X
3
+ X + 1
This signature compactor is used to compress serial data
shifted in from the local scan chain, into a 16-bit signature.
This signature can then be shifted out for comparison with an
expected value. This allows users to test long scan chains in
parallel, via Broadcast or Multi-Cast addressing modes, and
check only the 16-bit signatures from each module. The
LFSR is initialized with a value of 0000 Hex upon reset.
32-BIT TCK COUNTER REGISTER:
The 32-bit TCK
counter register enables BIST testing that requires n TCK
cycles, to be run on a parked LSP while another ’STA111
port is being tested. The
CNTRSEL
instruction can be used
to load a count-down value into the counter register via the
active scan chain. When the counter is enabled (via the
CNTRON
instruction), and the LSP is parked, the local TCKs
will stop and be held low when terminal count is reached.
The TCK counter is initialized with a value of 00000000 Hex
upon reset.
TABLE 12. Dedicated GPIO Register
n
(HDL only)
BIT
Description
7
Input
6
Input
5
Input
4
Input
3
Output
2
Output
1
Output
0
Output
TABLE 13. Shared GPIO Register
n
BIT
Description
Used in Silicon
Default Value
7
Reserved
N
0
6
Reserved
N
0
5
Reserved
N
0
4
Reserved
N
0
3
Reserved
N
0
2
Input (TDI)
Y
0
1
Output (TDO)
Y
0
0
Output (TMS)
Y
0
S
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