參數(shù)資料
型號： SCANSTA111SM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： EMITTER IR 850NM 5MM RADIAL
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49
封裝： BGA-49
文件頁數(shù)： 15/29頁
文件大?。?/td> 524K
代理商： SCANSTA111SM
Level 2 Protocol
(Continued)
’STA111s connected to the backplane. The
PARKPAUSE
instruction is scanned into the selected ’STA111s and the
’STA111 TAP controllers are sequenced to the
Pause-DR
state where the LSPs of all ’STA111s become unparked. The
local TAP controllers are then sequenced through the
Update-DR
,
Select-DR
,
Capture-DR
,
Exit1-DR
, and parked
in the
Pause-DR
state, as the ’STA111 TAP controller is
sequenced into the
Update-DR
state. When a LSP is parked,
it is removed from the active scan chain.
GOTOWAIT:
This instruction is used to return all ’STA111s to
the
Wait-For-Address
state. All unparked LSPs will be
parked in the
Test-Logic-Reset
TAP controller state (see
Figure 5
).
MODESEL:
The
MODESEL
instruction inserts Mode Regis-
ter
into the active scan chain. Mode Register
determines
the LSPN configuration for a device with up to five (5) LSPs
(only three in Silicon). Bit 7 of Mode Register
0
is a read-only
counter status flag.
MODESEL
n
:
The
MODESEL
instruction inserts Mode Reg-
ister
(n = 1 to 3) into the active scan chain. Mode Register
1
determines the LSPN configuration for LSP 5, 6 and 7 (if
they exist), and Mode Register
2
determines the Shared
GPIO configuration.
MCGRSEL:
This instruction inserts the multi-cast group reg-
ister (MCGR) into the active scan chain. The MCGR is used
to group ’STA111s into multi-cast groups for parallel TAP
sequencing (i.e., to simultaneously perform identical scan
operations).
SOFTRESET:
This instruction causes all 3 Port configura-
tion controllers (see
Figure 4
) to enter the
Parked-TLR
state,
which forces TMS
n
high; this parks each local port in the
Test-Logic-Reset
state within 5 TCK
B
cycles.
LFSRSEL:
This instruction inserts the linear feedback shift
register (LFSR) into the active scan chain, allowing a com-
pacted signature to be shifted out of the LFSR during the
Shift-DR
state. (The signature is assumed to have been
computed during earlier
LFSRON
shift operations.) This in-
struction disables the LFSR register’s feedback circuitry,
turning the LFSR into a standard 16-bit shift register. This
allows a signature to be shifted out of the register, or a seed
value to be shifted into it.
LFSRON:
Once this instruction is executed, the linear feed-
back shift register samples data from the active scan path
(including all unparked TDI
) during the
Shift-DR
state. Data
from the scan path is shifted into the linear feedback shift
register and compacted. This allows a serial stream of data
to be compressed into a 16-bit signature that can subse-
quently be shifted out using the
LFSRSEL
instruction. The
linear feedback shift register is not placed in the scan chain
during this mode. Instead, the register samples the active
scan-chain data as it flows from the LSPN to TDO
B
.
LFSROFF:
This instruction terminates linear feedback shift
register sampling. The LFSR retains its current state after
receiving this instruction.
CNTRSEL:
This instruction inserts the 32-bit TCK counter
shift register into the active scan chain. This allows the user
to program the number of n TCK cycles to send to the parked
local ports once the
CNTRON
instruction is issued (e.g., for
BIST operations). Note that to ensure completion of count-
down, the ’STA111 should receive at least n TCK
B
pulses.
CNTRON:
This instruction enables the TCK counter. The
counter begins counting down on the first rising edge of
TCK
following the
Update-IR
TAP controller state and is
decremented on each rising edge of TCK
thereafter. When
the TCK counter reaches terminal count, 00000000 Hex,
TCK
of all parked LSP’s is held low. This function overrides
Mode Register
0
TCK control bit (bit-3).
If the
CNTRON
instruction is issued when the TCK counter is
00000000 (terminal count) the local TCKs of parked LSPs
will be gated. The counter will begin counting on the rising
edge of TCK
when the TCK counter is loaded with a non-
zero value following a
CNTRSEL
instruction (see BIST Sup-
port in Special Features section for an example).
CNTROFF:
This instruction disables the TCK counter, and
TCK
n
control is returned to Mode Register
0
(bit-3).
DEFAULT_BYPASS:
This instruction selects the Bypass
register to be the default for SCANSTA111 commands that
do not explicitly require a data register. The default after
RESET is the Device ID register.
10124512
FIGURE 9. Local Scan Port Synchronization from Parked-TLR State
S
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SCANSTA111SM/NOPB 功能描述:接口 - 專用 Enhanced SCAN Bridge Multidrop Port RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA111SMX 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA111SMX/NOPB 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA112 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer
SCANSTA112_05 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer
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