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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Serial Scan Interface (SSI)
(Continued)
WRITING A PARTIAL BYTE TO THE TMS0, TMS1 OR
TDO SHIFTER/BUFFER.
Since the TMS0, TMS1 and TDO
shifter/buffers shift out least significant bit first, the valid
(meaningful) bits within a partial byte (i.e., byte containing
<
8 valid bits to be shifted to the scan chain) must be stored
and written into the shifter/buffer as the least significant bits.
This will assure that the desired bits will be accurately shifted
to the boundary scan chain. For example, moving the TAP
controllers within the boundary scan chain connected to
TMS0 from the Pause-DR state to the Run-Test/Idle state re-
quires a 3-bit (110) sequence on TMS0. To provide correct
3-bit sequence on TMS0, the partial byte would be written to
the TMS0 shifter/buffer as:
MSB
LSB
→
x
x
x
x
x
0
1
1
TMS0
A subsequent enable and load of CNT32 with decimal 3 and
enable of the TMS0 shifter/buffer will initialize the shift opera-
tion. Terminal count on CNT32 will complete the shift opera-
tion. Since terminal count on CNT32 will cause the register
selection to change within the shifter/buffer, the values la-
beled as “x” will not be used and are treated as “don’t cares”.
TDI SHIFTER/BUFFER
The TDI Shifter/Buffer block diagram is shown in Figure 13
This block shifts in serial data from the TDI port and puts it in
parallel form for read operations at the PPI. During normal
shift modes, double-buffering is achieved by configuring the
shifter/buffer as a 2 x 8 FIFO. This block can also be config-
ured as a 16-bit Serial Signature Compactor (SSC). Write,
read, and shift operations are controlled by a local state ma-
chine that accepts stimulus from the PPI, Mode Registers,
CNT32 and the TCK Control section. The TDI input always
shifts in data on the rising edge of SCK. The order of shifting
is least significant bit first. The TDI input includes a pull-up
resistor to force a logic 1 when the test data signal returning
from the scan chain is floating.
Read operations are completed if the shifter/buffer is not
empty and SSC mode is not enabled. Otherwise they are ig-
nored. Write operations are only possible while in SSC
mode. Otherwise they are ignored.
Shifting occurs when the following conditions are all true:
Local select circuitry is used to toggle back and forth be-
tween the two registers of the “FIFO” when shifting. At any
given time, one register is selected for shift operations. The
other holds its previous state or can accept new serial data.
Shift register selection changes due to the following two
events:
CNT3 in TCK Control signals that 8 bits have been
shifted in. This event is used for basic toggling between
each of the two shift registers.
CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
signal, a partial byte (i.e., byte with
<
eight valid data bits
shifted from the scan chain) will exist in the correspond-
ing shift register. The embedded test software functions
written to support the evaluation of data read from the
TDI shifter/buffer must consider bit placement when
reading and evaluating a partial byte.
READING A PARTIAL BYTE FROM THE TDI SHIFTER/
BUFFER.
Data is shifted from the scan chain into each TDI
register from most significant bit to least significant bit. Con-
sequently, the valid (i.e., meaningful) bits in a partial byte
shifted into a TDI register will reside in the upper significant
bit locations. For example, if a scan operation involves shift-
ing and evaluating 53 bits returning to TDI, TDI shifter/buffer
must be read 7 times (i.e., 6 full bytes plus a partial byte con-
taining 5 meaningful bits). If the last 5 bits shifted back to the
TDI shifter/buffer are 11010, then upon completion of the
shift operation (i.e., terminal count on CNT32), the shift reg-
ister within the TDI shifter/buffer will contain the following
partial byte:
TDI is enabled with its respective mode bit.
TDI shifter/buffer is not full.
TCK is enabled according to the logic in TCK Control.
MSB
LSB
TDI
Following a read of a partial byte, the embedded test soft-
ware must adjust the position of the valid bits read from the
TDI shifter/buffer or the position of the expected data to as-
sure that an accurate comparison is made (and the
non-meaningful bits are masked).
→
0
1
0
1
1
x
x
x
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