參數(shù)資料
型號(hào)： SCANPSC100F
廠商： National Semiconductor Corporation
英文描述： Embedded Boundary Scan Controller(嵌入式邊界掃描控制器)
中文描述： 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器）
文件頁(yè)數(shù)： 11/25頁(yè)
文件大?。?/td> 364K
代理商： SCANPSC100F
Serial Scan Interface (SSI)
(Continued)
TDI Shifter/Buffer is enabled in SSC mode but is not fully
loaded with an initial value.
TMS0 Shifter/Buffer is enabled and empty.
TMS1 Shifter/Buffer is enabled and empty.
CNT32 is enabled but not loaded.
CNT32 is enabled and has reached terminal count.
Also included within the TCK control block in CNT3, a 3-bit
count up counter. CNT3 is included to maintain byte align-
ment within the shifter/buffers by providing a signal to toggle
between the two 8-bit FIFOs which comprise the shifter/
buffer. The toggling operation occurs, in an enabled shifter/
buffer, each time CNT3 counts 8 TCK cycles or when CNT32
reaches terminal count. The CNT3 is reset to 0 when CNT32
reaches terminal count or after a PSC100 reset condition.
FREEZE MODE.
This mode is included in the TCK control
block to support the 1149.1 SAMPLE operation. The intent of
the SAMPLE instruction is to allow device input and output
levels to be observed during normal system operation. Data
is latched (or “sampled”) into the boundary scan registers
when the TAP controller (see Figure 8 on previous page)
transitions from the Capture-DR state to the Shift-DR state (if
SAMPLE/ PRELOAD is the active instruction). Synchroniz-
ing this “transition” (rising edge of TCK with TMS at logic low)
with a known system state is imperative to an accurate pass/
fail assessment. The Freeze Mode provides a means of
asynchronously creating the TCK pulse via an external
PSC100 pin. When the Freeze Pin Enable bit (bit 2 in Mode
Register 1) is set, a logic high on the PSC100 FRZ input pin
will cause TCK to go high. Once the transition is complete,
the Freeze Mode can be removed (i.e. Freeze Pin Enable bit
returned to logic 0 or Freeze pin forced low) and the sampled
data can be shifted out/evaluated using the “standard”
PSC100 protocol. Figure 9 illustrates the logic implementa-
tion of the Freeze feature. It should be noted that Freeze
mode is simply gated with the TCK output and does not dis-
able shift operations within the shifter/buffers or disable
CNT32. Therefore, no shifting or TCK counting using CNT32
should be performed when Freeze mode is enabled.
The “standard” mode of TCK control uses CNT32 in conjunc-
tion with the status registers to start and stop TCK. For this
mode, CNT32 is enabled and loaded with the number of
TCK cycles required to shift the desired bits to/from the scan
chain. The shifter/buffer(s) participating in the shift operation
is enabled and provides the necessary full/empty status to
stop TCK for processor writes/reads. This mode of TCK con-
trol provides a systematic protocol for managing PSC100
operations (specifically, handling partial bytes). Another op-
tion for TCK control relies solely on the status of the shifter/
buffers (i.e., CNT32 is disabled) to start and stop TCK. This
option eliminates the time required to load CNT32, but
makes management of partial bytes (see shifter/buffer de-
scription section) more cumbersome.
TMS(1:0) SHIFTER/BUFFERS
The TMS Shifter/Buffer block diagram is shown in Figure 10
These two blocks take parallel data and serialize it for shift
operations through the serial port pins TMS0 and TMS1.
Double-buffering is achieved by configuring the shifter/buffer
as a 2 x 8 FIFO. Write and shift operations are controlled by
a local state machine that accepts stimulus from the PPI,
Mode Registers, CNT32 and TCK Control section. The TMS
outputs always change on the falling edge of SCK. The order
of shifting is least significant bit first. TMS(1:0) are forced
high upon RST low. TMS(1:0) are TRI-STATEd when OE is
high.
Write operations are completed if the shifter/buffer is not full
(independent of whether shifter/buffer is enabled or dis-
abled). Otherwise they are ignored. Shifting occurs when the
following conditions are all true:
TMS is enabled with its respective mode bit.
TMS shifter/buffer is not empty.
DS100325-9
FIGURE 9. TCK Logic
DS100325-10
FIGURE 10. TMS Shifter/Buffer Block Diagram
www.national.com
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