參數(shù)資料
型號(hào)： SCAN928028TUF
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 通用總線功能
英文描述： 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST
中文描述： OCTAL LINE DRIVER, PBGA196
封裝： LBGA-196
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 376K
代理商： SCAN928028TUF
Functional Description
(Continued)
back path from the deserializer to the serializer. This feed-
back path can be as simple as connecting the deserializer’s
LOCK pin to the serializer’s SYNC pin. This will automati-
cally signal the serializers to send SYNC patterns whenever
the deserializer loses lock.
The user has the choice of allowing the deserializer to re-
synchronize to the data stream, or to force synchronization
by pulsing the Serializer SYNC pin. This scheme is left up to
the user discretion.
POWER-DOWN
The Power-down state is a low power sleep mode that the
Serializer and Deserializer typically occupy while waiting for
initialization, or to reduce power when there are no pending
data transfers. The SCAN928028 serializers enter Power-
down when MS_PWDN is driven low. In Power-down, the
PLLstops and the outputs go into TRI-STATE. To exit Power-
down, the system drives MS_PWDN high.
Each of the serializers in the ’8028 also has an individual
power down, PWDNn control pin. This control enables the
deactivation of individual serializers while allowing others to
operate normally. The benefit is that spare serializers can be
allocated for backup operation, but not consuming power
until employed for data transfers.
The Individual Power Down will NOT cause the PLL of the
device to lose lock, but it will cause the specific serializer
channel to go into a low power sleep mode and its output go
into TRI-STATE. Thus, the device will NOT go through the
Initialization state when individual channels exit the Indi-
vidual Power Down state, and the output of the specific
channel will become available after a short delay, see
Figure
7
and spec t
ICR
TRI-STATE
When the system drives DEN pin low, the serializer outputs
enter TRI-STATE. This will TRI-STATE the output pins
(DO0
±
to DO7
±
). When the system drives DEN high, the
serializers will return to the previous state as long as all other
control pins remain static (PWDNn, TCLK, SYNCn, and
DINn[0:9]).
TEST FEATURES
Since the high-speed LVDS serial data transmission line
quality is essential to the chipset operation, a means of
checking this signal integrity is built into the SCAN928028
serializer. Each Serializer channel has the ability to transfer
an internally generated PRBS data pattern. This pattern
traverses the transmission line to the deserializer. Specific
deserializers (SCAN921224 for example) have the comple-
ment PRBS pattern verification circuit. The deserializer
checks the data pattern for bit errors and reports any errors
on the test verification pins on the deserializer.
The
@
SPEED feature uses 5 signal pins. The BIST_SEL[0:3]
and BIST_ACT pins together determine the functions of the
BIST mode. The BIST_ACT signal activates the test feature.
The BIST_SEL[0:3] selects 1 of 8 channels as the output for
the BIST pattern. All channels perform BIST when BIS-
T_ACT = H and BIST_SEL
<
0:3
>
=08H.
JTAG TEST FEATURES
In addition to using IEEE 1149.1 test access to the digital
TTL pins, the SCAN928028 has two instructions to test the
LVDS interconnects. The first instruction is EXTEST. This is
implemented at LVDS levels and is only intended as a go
no-go test (e.g. missing cables). The second method is the
RUNBIST instruction. It is an "at-system-speed" interconnect
test. It is executed in approximately 33mS with a maximum
system clock speed of 66MHz. There are two bits in the RX
BIST data register for notification of PASS/FAIL and
TEST_COMPLETE. Pass indicates that the BER (Bit-Error-
Rate) is better than 10
-7
.
An important detail is that once both devices have the RUN-
BIST instruction loaded into their respective instruction reg-
isters, both devices must move into the RTI (
Run-Test-Idle
)
state within 4K system clocks (At a TCLK of 66Mhz and TCK
of 1MHz this allows for 66 TCK cycles). This is not a concern
when both devices are on the same scan chain or LSP,
however, it can be a problem with some multi-drop devices.
This test mode has been simulated and verified using Na-
tional’s SCANSTA111.
If the user is unable to meet the constraint of moving both
taps into RTI within 4K system clocks, the receiver must be
moved into the RTI state first. The receiver can then stay in
RTI indefinitely until the transmitter is moved into RTI and the
BIST pattern begins. This is true for either SCAN initiated
BIST or pin initiated BIST_ALONE or any combination of the
two.
S
www.national.com
10
相關(guān)PDF資料
PDF描述
SCAN928028TUFX 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST
SCAN92LV090 9 Channel Bus LVDS Transceiver with 1149.1 Access
SCAN92LV090SLC 9 Channel Bus LVDS Transceiver w/ Boundary SCAN
SCAN92LV090VEH HEATSINK TO-220 H=2.5 BLK W/PIN
SCANPSC100F Embedded Boundary Scan Controller(嵌入式邊界掃描控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SCAN928028TUF/NOPB 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SCAN928028TUFX 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SCAN928028TUFX/NOPB 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SCAN92LV090 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:9 Channel Bus LVDS Transceiver with 1149.1 Access
SCAN92LV090_06 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:9 Channel Bus LVDS Transceiver w/ Boundary SCAN
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*