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參數(shù)資料
| 型號(hào)： | SCAN921260UJB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | SCAN921260UJB |
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Application Information
(Continued)
all input control cases including PWRDN and REN. In addi-
tion to the 4 required Test Access Port (TAP) signals of TMS,
TCK, TDI, and TDO, TRST is provided for test reset.
To supplement the test coverage provided by the IEEE
1149.1 test access to the digital TTL pins, the SCAN921260
has two instructions to test the LVDS interconnects. The first
is EXTEST. This is implemented at LVDS levels and is only
intended as a go no-go test (e.g. missing cables). The sec-
ond method is the RUNBIST instruction. It is an "at-system-
speed" interconnect test. It is executed in approximately
33mS with a system clock speed of 66MHz. There are 12
bits in the RX BIST data register for notification of PASS/
FAIL and TEST_COMPLETE; two bits for each of the six
channels. The RX BIST register is defined as (from MSB to
LSB):
[BIST COMPLETE for Channel 6, BIST PASS/FAIL for
Channel 6, BIST COMPLETE for Channel 5, BIST PASS/
FAIL for Channel 5, BIST COMPLETE for Channel 4, BIST
PASS/FAIL for Channel 4, BIST COMPLETE for Channel 3,
BIST PASS/FAIL for Channel 3, BIST COMPLETE for Chan-
nel 2, BIST PASS/FAIL for Channel 2, BIST COMPLETE for
Channel 1, BIST PASS/FAIL for Channel 1]
A "pass" indicates that the BER (Bit-Error-Rate) is better
than 10
-7
. This is a minimum test, so a "fail" indication means
that the BER is higher than 10
-7
.
The BIST features of the SCAN921260 six (6) channel de-
serializer are compatible with the BIST features on the
SCAN921023 Serializer.
An important detail is that once both devices have the RUN-
BIST instruction loaded into their respective instruction reg-
isters, both devices must move into the RTI state within 4K
system clocks (At a system CLK of 66Mhz and TCK of 1MHz
this allows for 66 TCK cycles). This is not a concern when
both devices are on the same scan chain or LSP, however, it
can be a problem with some multi-drop devices. This test
mode has been simulated and verified using National’s
SCANSTA111.
Typical applications of 1149.1 are based around TTL-type
inputs. With the introduction of 1149.1 into LVDS there have
been many hurdles to overcome. One issue is that TTL
inputs and outputs do not require bias circuits and are al-
ways on when power is applied. In the case of LVDS, there
are many circuits required to make the inputs and outputs
achieve their tight tolerances. These circuits require settle
time once power is applied to ensure they function properly.
These circuits are also the largest users of power within the
device. To reduce power in standby, these devices have a
PWRDN pin to shut these circuits down. There is also a REN
pin that enables/disables the TTL outputs.
In the case of the 1149.1 functionality, these circuits need
appropriate time to stabilize before they can be utilized. To
achieve stability, these circuits are powered up when the
TAP controller state machine is not in the
Test-Logic-Reset
state. The time that it takes a TAP to traverse from
Test-
Logic-Reset
to
Capture-Data-Register
running at 25MHz is
sufficient to allow these circuits to stabilize.
Once the TAP has left
Test-Logic-Reset
, the internal value of
PWRDN is overridden and the device is powered up. This
includes all fore mentioned circuits as well as all outputs. If
an application requires that the outputs are to remain dis-
abled during 1149.1 test, use REN and not PWRDN.
KNOWN ERRATA: On the SCAN921260 only the overridden
value of PWRDN ("1") is captured during all 1149.1 tests and
not the external value as seen on the pin.
BIST ALONE TEST MODES
The SCAN921260 also supports a BISTAlone feature which
can be run without enabling the JTAG TAP controller. This
feature provides the ability to run continuos BER testing on
all channels, or on individual channels without affecting live
traffic on other channels. The ability to run the BERT while
adjacent channels are carrying normal traffic is a useful tool
to determine how normal traffic will affect BER on any given
channel.
The BIST Alone features can be accessed using the 5 pins
defined as BIST_SEL0, BIST_SEL1, BIST_SEL2, BIS-
T_ACT, and BISTMODE_REQ.
BIST_ACT activates the BIST Alone mode. The BIST Alone
mode will continue until deactivated by the BIST_ACT pin.
The BIST_ACT input must be high or low for 4 or more clock
cycles in order to activate or deactivate the BIST Alone
mode. The BIST_ACT input is pulled low internally.
BISTMODE_REQ is used to select either gross error report-
ing or a specific output error report. When the BIST Alone
mode is active, the LOCK(1:6) output for all channels run-
ning BIST Alone will go low, and ROUT(0:9) reports any
error. When BISTMODE_REQ is low the error reporting is
set to Gross Mode, and whenever a bit contains one or more
errors, ROUT(0:9) for that channel goes high and stays high
until deactivation by the BIST_ACT input. When BISTMOD-
E_REQ is high, the output error reporting is set to Bit Error
mode. Whenever any data bit contains an error, the data
output for that corresponding bit goes high. The default is
Gross Error mode.
The three BIST_SELn inputs determine which channel is in
BIST Alone mode according to the following table:
S
www.national.com
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| SCAN926260 | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJBX | 功能描述:IC DESERIALIZER X6 1:10 196-LBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:SCAN 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| SCAN921821 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| SCAN921821TSM | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921821TSM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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