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參數(shù)資料
| 型號： | SCAN921260UJB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 379K |
| 代理商： | SCAN921260UJB |
Application Information
USING THE SCAN921023 and SCAN921260
The SCAN921260 combines six 1:10 deserializers into a
single chip. Each of the six deserializers accepts a BusLVDS
data stream up to 660 Mbps from National Semiconductor’s
SCAN921023 Serializer. The deserializers then recover the
embedded two clock bits and data to deliver the resulting
10-bit wide words to the output. A seventh serial data input
provides n+1 redundancy capability. The user can program
the seventh input to be an alternative input to any of the six
deserializers. Whichever input is replaced by the seventh
input is then routed to the CHANNEL TEST (CHTST) pin on
receiver output port. The Deserializer uses a separate refer-
ence clock (REFCLK) and an onboard PLL to extract the
clock information from the incoming data stream and then
deserialize the data. The Deserializer monitors the incoming
clock information, determines lock status, and asserts the
LOCKn output high when loss of lock occurs.
Each of the 6 channels acts completely independent of each
other. Each independent channel has outputs for a 10-bit
wide data word, the recovered clock out, and the lock-detect
output.
The SCAN921260 has three operating states: Initialization,
Data Transfer, and Resynchronization. In addition, there are
two passive states: Powerdown and TRI-STATE.
The following sections describe each operating mode and
passive state.
INITIALIZATION
Before the SCAN921260 receives and deserializes data, it
and the transmitting serializer devices must initialize the link.
Initialization refers to synchronizing the Serializer’s and the
Deserializer’s PLL’s to local clocks. The local clocks must be
the same frequency or within a specified range if from differ-
ent sources. After all devices synchronize to local clocks, the
Deserializers synchronize to the Serializers as the second
and final initialization step.
Step 1: After applying power to the Deserializer, the outputs
are held in TRI-STATE and the on-chip power-sequencing
circuitry disables the internal circuits. When V
reaches
V
OK (2.1V), the PLL in each deserializer begins locking to
the local clock (REFCLK).Alocal on-board oscillator or other
source provides the specified clock input to the REFCLK pin.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. Refer to the Serializer
data sheet for the proper operation during this step of the
Initialization State. The Deserializer identifies the rising clock
edge in a synchronization pattern or random data and after
80 clock cycles will synchronize to the data stream from the
serializer. At the point where the Deserializer’s PLL locks to
the embedded clock, the LOCKn pin goes low and valid data
appears on the output. Note that this differs from previous
deserializers where the LOCKn signal was not synchronous
to valid data appearing on the outputs.
DATA TRANSFER
After initialization, the serializer transfers data to the deseri-
alizers. The serial data stream includes a start and stop bit
appended by the serializer, which frame the ten data bits.
The start bit is always high and the stop bit is always low.
The start and stop bits also function as clock bits embedded
in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at
12 times the TCLK frequency. For example, if TCLK is 40
MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10
bits are from input data, the serial ’payload’ rate is 10 times
the TCLK frequency. For instance, if TCLK = 40 MHz, the
payload data is 40 X 10 = 400 Mbps. TCLK is provided by
the data source and must be in the range 20 MHz to 40 MHz
nominal.
When one of six Deserializer channels synchronizes to the
input from a Serializer, it drives its LOCKn pin low and
synchronously delivers valid data on the output. The Dese-
rializer locks to the embedded clock, uses it to generate
multiple internal data strobes, and drives the embedded
clock to the RCLKn pin. The RCLKn is synchronous to the
data on the ROUT[n0:n9] pins. While LOCKn is low, data on
ROUT [n0:n9] is valid. Otherwise, ROUT[n0:n9] is invalid.
All ROUT, LOCK, and RCLK signals will drive a minimum of
three CMOS input gates (15pF load) with a 66 MHz clock.
This amount of drive allows bussing outputs of two Deseri-
alizers and a destination ASIC. REN controls TRI-STATE of
all the outputs.
The Deserializer input pins are high impedance during Pow-
erdown (PWRDN low) and power-off (V
cc
= 0V).
RESYNCHRONIZATION
Whenever one of the six Deserializers loses lock, it will
automatically try to resynchronize. For example, if the em-
bedded clock edge is not detected two times in succession,
the PLL loses lock and the LOCKn pin is driven high. The
system must monitor the LOCKn pin to determine when data
is valid.
The user has the choice of allowing the deserializer to re-
synch to the data stream or to force synchronization by
pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is
left up to the user discretion. One recommendation is to
provide a feedback loop using the LOCKn pin itself to control
the sync request of the Serializer (SYNC1 or SYNC2). Dual
SYNC pins are given for multiple control in a multi-drop
application.
POWERDOWN
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer typically occupy while waiting for
initialization, or to reduce power consumption when no data
is transferred. The Deserializer enters Powerdown when
PWRDN is driven low. In Powerdown, the PLL stops and the
outputs go into TRI-STATE, which reduces supply current to
the microamp range. To exit Powerdown, the system drives
PWRDN high.
Upon exiting Powerdown, the Deserializer enters the Initial-
ization state. The system must then allow time to Initialize
before data transfer can begin.
TRI-STATETRI-STATE
When the system drives REN pin low, the Deserializer enters
TRI-STATE. This will TRI-STATE the receiver output pins
(ROUT[00:59]) and RCLK[0:5]. When the system drives
REN high, the Deserializer will return to the previous state as
long as all other control pins remain static (PWRDN).
IEEE 1149.1 TEST MODES
The SCAN921260 features interconnect test access that is
compliant to the IEEE 1149.1 Standard for Boundary Scan
Test (JTAG).All digital TTL I/O’s on the device are accessible
using IEEE 1149.1, and entering this test mode will override
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJBX | 功能描述:IC DESERIALIZER X6 1:10 196-LBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:SCAN 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| SCAN921821 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| SCAN921821TSM | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921821TSM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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