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參數(shù)資料
| 型號： | SCAN921260UJB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 379K |
| 代理商： | SCAN921260UJB |
Application Information
(Continued)
Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes.
Surface mount capacitors placed close to power and
ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.001
μF to 0.1 μF. Tantalum capacitors may be in the range 2.2
μF to 10 μF. Voltage rating for tantalum capacitors should
be at least 5X the power supply voltage being used.
Randomly distributed by-pass capacitors should also be
used.
Package and pin layout permitting, it is also recom-
mended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the
interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending
the effective frequency range of the bypass components.
Leave unused Bus LVDS receiver inputs open (floating).
Isolate TTL signals from Bus LVDS signals.
There are more common practices which should be followed
when designing PCBs for BLVDS/LVDS signaling. General
application guidelines are available in the LVDS Owner’s
Manual (www.national.com/lvds). For packaging information
on BGA’s, please see AN-1126.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configurations, through PCB trace, or through twisted
pair cable. In point-to-point configurations, the transmission
media need only be terminated at the receiver end. Please
note that in point-to-point configurations, the potential of
offsetting the ground levels of the Serializer vs. the Deseri-
alizer must be considered. Also, Bus LVDS provides a +/
1.2V common mode range at the receiver inputs.
FAILSAFE BIASING FOR THE SCAN921260
The SCAN921260 has internal failsafe biasing and an im-
proved input threshold sensitivity of +/ 50mV versus +/
100mV for the DS92LV1210 or DS92LV1212. This allows for
greater differential noise margin in the SCAN921260. How-
ever, in cases where the receiver input is not being actively
driven, the increased sensitivity of the SCAN921260 can
pickup noise as a signal and cause unintentional locking. For
example, this can occur when the input cable is discon-
nected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. The pull-up and pull-down
resistors (R
and R
) provide a current path through the
termination resistor (R
) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see
Figure 8
for the Failsafe
Biasing Setup.
The parameter t
is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling.After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called t
. It is the offset from t
DJIT(min or max)
for the test
mask within the eye opening.
The vertical limits of the mask are determined by the
SCAN921260 receiver input threshold of +/ 50mV.
Please refer to the eye mask pattern of
Figure 9
for a graphic
representation of t
DJIT
and t
RNM
.
20014727
FIGURE 8. Failsafe Biasing Setup
S
www.national.com
11
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| SCAN926260 | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJBX | 功能描述:IC DESERIALIZER X6 1:10 196-LBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:SCAN 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| SCAN921821 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| SCAN921821TSM | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921821TSM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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