參數(shù)資料
型號(hào): SC28L202A1D
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 2 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153EE, SOT-364-1, TSSOP-56
文件頁(yè)數(shù): 67/77頁(yè)
文件大小: 531K
代理商: SC28L202A1D
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
61
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5 ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Test conditions for outputs: C
L
= 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50 pF, R
L
= 2.7K ohm to V
CC
.
4. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. Guaranteed by characterization of sample units.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t RWD time to guarantee that any status register changes are valid.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should be symmetrical.
RESETN
t
RES
SD00133
Figure 1. Reset Timing (80XXX mode)
A0–A3
CEN
t
AS
t
CS
t
CH
RDN
t
RW
t
RWD
D0–D7
(READ)
t
DD
t
DF
FLOAT
FLOAT
VALID
NOT
VALID
WDN
t
RWD
VALID
D0–D7
(WRITE)
t
DS
t
DH
t
AH
SD00087
Figure 2. Bus Timing (80XXX mode)
RESETN
t
RES
SD00109
Figure 3. Reset Timing (68XXX mode)
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