參數(shù)資料
型號: SC28L202A1D
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 2 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153EE, SOT-364-1, TSSOP-56
文件頁數(shù): 44/77頁
文件大?。?/td> 531K
代理商: SC28L202A1D
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
38
BCRx – Bidding Control Register – Xon/Xoff, A and B
Bits 7:0
MSBs of an Xon/Xoff interrupt bid
This register provides the 8 MSBs of the Interrupt Arbitration number for a Xon/Xoff interrupt.
BCRA – Bidding Control Register – Address, A and B
Bits 7:0
MSBs of an address recognition event interrupt bid
This register provides the 8 MSBs of the Interrupt Arbitration number for an address recognition event interrupt.
BCR C/T – Bidding Control Register –C/T, 0 and 1
Bits 7:0
MSBs of a counter/timer event interrupt bid
This register provides the 8 MSBs of the Interrupt Arbitration number for a counter/timer event interrupt.
BCRLBE – Bidding Control Register – Received Loop Back Error
Bits 7:0
MSBs of a received loop back error event interrupt bid
This register provides the 8 MSBs of the Interrupt Arbitration number for the received loop back error interrupt.
Registers of the I/O ports
IPCRL – Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B)
Bit 7
Bit 6
Bit 7
I/O3 n
change
change
change
0 = no change
1 = change
1 = change
1 = change
Bit 6
I/O0 n
change
0 = no change
1 = change
Bit 3
I/O3 n state
Bit 2
I/O2 n state
Bit 1
I/O1 n state
Bit 0
I/O0 n
state
I/O2 n
I/O1 n
0 = no change
0 = no change
Reads the actual logic level at the pin.
1 = high level; 0 = low level
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each
pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.
IPCRU – Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B)
Bit 7
Bit 6
Bit 7
I/O7 n change
I/O6 n change
I/O5 n change
0 = no change
1 = change
1 = change
1 = change
Bit 6
I/O4 n change
0 = no change
1 = change
Bit 3
I/O7 n state
Reads the actual logic level at the pin.
1 = high level; 0 = low level
Bit 2
I/0n6 state
Bit 1
I/O5 n state
Bit 0
I/O4 n state
0 = no change
0 = no change
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each
pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.
IPR – Input Port Register, A and B (n = A for A, n = B for B)
Bits 7:0
Logical levels of I/O(7:0)n
IPCE – Input Change Detect Enable, A and B (n = A for A, n = B for B)
Bit 7
Bit 6
Bit 5
I/O7 n enable
I/O6 n enable
I/O5 n enable
0 = disable
1 = enable
1 = enable
1 = enable
Bit 4
I/O4 n enable
0 = disable
1 = enable
Bit 3
I/O3 n enable
0 = disable
1 = enable
Bit 2
I/O2 n enable
0 = disable
1 = enable
Bit 1
I/O1 n enable
0 = disable
1 = enable
Bit 0
I/O0 n enable
0 = disable
1 = enable
0 = disable
0 = disable
IPCE[7:0] bits activate the input change of state detectors. If a pin is configured as an output, the change of state detectors, if enabled, continue
to be active and will show a change of state as the I/P port changes.
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